DRA821U-Q1: Serdes support in uboot

Nikhil k

Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821

Tool/software:

Hi Team,

We are working on DRA821 CPU with Linux sdk 09.02. we want to test serdes feature in uboot, when we configured serdes in uboot, boot hangs and returns with below mentioned error.

cdns,torrent serdes@5060000: Timeout waiting for CMN ready
cdns,torrent serdes@5060000: PHY: Failed to power on serdes@5060000: -110.
phy_power_on failed!!: -110

So, is serdes validated in u-boot?. if yes, any additional changes am i missing

Note: All the dts and board/ti/j721e/evm.c file changes are done properly

Regards,

Nikhil K

4 months ago

0 Tanmay Patil 4 months ago

TI__Mastermind 30450 points

Hi Nikhil,

What is your serdes configuration?

Nikhil k said:
So, is serdes validated in u-boot?. if yes, any additional changes am i missing

By default, for j7200, PCIe and SGMII links are configured in serdes. So yes, some configurations are supported from u-boot. But not all are supported.

Regards,
Tanmay

0 Nikhil k 4 months ago in reply to Tanmay Patil

Intellectual 260 points

Hi Tanmay,

We want to test USB3.0 in uboot(usb3.0 signals from serdes LANE4).

This is my dts settings

&serdes0 {
        status="okay";
        serdes0_usb_link: phy@1 {
                reg = <3>;
                cdns,num-lanes = <1>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_USB3>;
                resets = <&serdes_wiz0 4>;
        };
};

&usb0 {
        dr_mode = "host";
        phy-names = "cdns3,usb3-phy";
        phys = <&serdes0_usb_link>;
        status="okay";
};

&serdes_ln_ctrl {
        status="okay";
        idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
                      <J7200_SERDES0_LANE2_IP4_UNUSED>, <J7200_SERDES0_LANE3_USB>;
};

&usb_serdes_mux {
        idle-states = <1>; /* USB0 to SERDES lane 3 */
};

in board/ti/j721e/evm.c file im enabling "configure_serdes_torrent()" function, in this function i'm observing while doing phy power on (generic_phy_power_on()) facing the failure as mentioned earlier.

Seems like this is not related to usb settings, serdes itself not getting activated.

Note: In kernel we able to test this feature successfully, but i enable serdes in uboot in kernel also im observing same error.

Regards,

Nikhil K

0 Tanmay Patil 3 months ago in reply to Nikhil k

TI__Mastermind 30450 points

Hi Nikhil,

By default serdes on j7200 is used for PCIe+QSGMII. To use USB on the same serdes, you would have to remove one of them, either PCIe or QSGMII. From the looks of it, based on your serdes_lane_ctrl, you have removed QSGMII. But you also have to remove the node in device-tree for QSGMII link. Can you confirm that you have done this?

Apart from this can you ensure the USB configs are present for u-boot?

For other devices, USB is tested at u-boot.

Regards,
Tanmay

0 Nikhil k 3 months ago in reply to Tanmay Patil

Intellectual 260 points

Hi Tanmay,

Thanks for the reply,

I have removed QSGMII entry from dts.

Also usb configuration looks fine compared to kernel

we have tested usb in 2.0 otg mode, that works properly, so the usb configuration are fine it seems.

But here serdes phy itself not probing...

Regards,

Nikhil K

0 Nikhil k 3 months ago in reply to Nikhil k

Intellectual 260 points

Hi Tanmay,

Is there any update on this case?

Regards,

Nikhil K

0 Nikhil k 3 months ago in reply to Nikhil k

Intellectual 260 points

Hi Tanmay,
Is there any update ?

Regards,

Nikhil K

0 Tanmay Patil 3 months ago in reply to Nikhil k

TI__Mastermind 30450 points

Hi Nikhil,

Sorry for the delay.

Nikhil k said:
But here serdes phy itself not probing..

Have you verified this with additional prints in the u-boot?

Can you share the complete updated device-tree with all the changes.

Regards,
Tanmay

0 Nikhil k 3 months ago in reply to Tanmay Patil

Intellectual 260 points

Tanmay Patil said:
Have you verified this with additional prints in the u-boot?

Yes, its failing below mentioned section in serdes driver

        /*
         * Wait for cmn_ready assertion
         * PHY_PMA_CMN_CTRL1[0] == 1
         */
        ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
                                             read_val, read_val, 1000,
                                             PLL_LOCK_TIMEOUT);
        if (ret) {
                dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
                return ret;
}

Find the dts changes

4150.k3-j7200-common-proc-board.txt

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

        aliases {
                i2c0 = &wkup_i2c0;
                i2c1 = &mcu_i2c0;
        };

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
                pinctrl-names = "default";
                pinctrl-0 = <&wkup_vdd_mmc1_pins_default>;
                gpio = <&wkup_gpio0 84 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv: gpio-regulator-sd-dv {
		compatible = "regulator-gpio";
		regulator-name = "vdd_sd_dev";
                pinctrl-names = "default";
                pinctrl-0 = <&main_vdd_sd_pins_default>;
                regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};
};

&main_gpio0 {
	status = "okay";
};

&wkup_pmx0 {

        wkup_eth_rst_pins_default: wkup_eth_rst_default_pins {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x24, PIN_OUTPUT_PULLUP, 7) /* (A8) MCU_OSPI0_D6.WKUP_GPIO0_25 */
                >;
        };
};

&wkup_pmx2 {
        status = "okay";

        mcu_i2c0_pins_default: mcu-i2c0-default-pins {
              pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x0A0, PIN_INPUT_PULLUP, 0) /* (G21) MCU_I2C0_SCL */
                        J721E_WKUP_IOPAD(0x0A4, PIN_INPUT_PULLUP, 0) /* (G20) MCU_I2C0_SDA */
                >;
        };
};

&wkup_pmx3 {
        status = "okay";

        wkup_vdd_mmc1_pins_default: wkup-vdd-mmc1-pins-default {
                pinctrl-single,pins = <
                        J721E_WKUP_IOPAD(0x1C, PIN_OUTPUT, 7) /* (E18) WKUP_GPIO0_84 */
                >;
        };
};

&main_pmx0 {
        status = "okay";

        main_vdd_sd_pins_default: main-vdd-sd-pins-default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x18, PIN_OUTPUT, 7) /* (V17) RMII1_TX_EN.GPIO0_7 */
			/*J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
                >;
        };
	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
		>;
	};
	
	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
		>;
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "reserved";
};

&main_uart0 {
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart2 {
	/* MAIN UART 2 is used by R5F firmware */
	status = "reserved";
};

&main_uart3 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart4 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart5 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart6 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart7 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart8 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio0 {
        status = "okay";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&wkup_gpio0 {
        status = "okay";
};

&wkup_gpio1 {
	status = "disabled";
};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	status="okay";
};

&main_sdhci1 {
	pinctrl-0 = <&main_mmc1_pins_default>;
	pinctrl-names = "default";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	status="okay";
};

&serdes_ln_ctrl {
	status="okay";
	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
		      <J7200_SERDES0_LANE2_IP4_UNUSED>, <J7200_SERDES0_LANE3_USB>;
};

&usb_serdes_mux {
	idle-states = <1>; /* USB0 to SERDES lane 3 */
};

&usbss0 {

	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "host";	
	phy-names = "cdns3,usb3-phy";
	phys = <&serdes0_usb_link>;
	status="okay";
};

&tscadc0 {
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&serdes_refclk {
	status="okay";
	clock-frequency = <100000000>;
};

&serdes0 {
	status="okay";
	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};

        serdes0_usb_link: phy@1 {
                reg = <3>;
                cdns,num-lanes = <1>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_USB3>;
                resets = <&serdes_wiz0 4>;
        };
};

&serdes_wiz0 {
	status = "okay";
};

&pcie1_rc {
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
	status="okay";
};

&pcie1_ep {
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
	status = "disabled";
};

&wkup_gpio0 {
	status = "okay";
};

k3-j7200-common-proc-board-u-boot.txt

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-j7200-binman.dtsi"

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		tick-timer = &timer1;
	};

	aliases {
		i2c0 = &wkup_i2c0;
		i2c1 = &mcu_i2c0;
	};
};

&cbass_main {
	bootph-pre-ram;
};

&main_navss {
	bootph-pre-ram;
};

&cbass_mcu_wakeup {
	bootph-pre-ram;

	timer1: timer@40400000 {
		compatible = "ti,omap5430-timer";
		reg = <0x0 0x40400000 0x0 0x80>;
		ti,timer-alwon;
		clock-frequency = <250000000>;
		bootph-pre-ram;
	};

	chipid@43000014 {
		bootph-pre-ram;
	};

	mcu_navss: bus@28380000 {
		bootph-pre-ram;
		#address-cells = <2>;
		#size-cells = <2>;

		ringacc@2b800000 {
			reg =	<0x0 0x2b800000 0x0 0x400000>,
				<0x0 0x2b000000 0x0 0x400000>,
				<0x0 0x28590000 0x0 0x100>,
				<0x0 0x2a500000 0x0 0x40000>,
				<0x0 0x28440000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
			bootph-pre-ram;
		};

		dma-controller@285c0000 {
			reg =	<0x0 0x285c0000 0x0 0x100>,
				<0x0 0x284c0000 0x0 0x4000>,
				<0x0 0x2a800000 0x0 0x40000>,
				<0x0 0x284a0000 0x0 0x4000>,
				<0x0 0x2aa00000 0x0 0x40000>,
				<0x0 0x28400000 0x0 0x2000>;
			reg-names = "gcfg", "rchan", "rchanrt", "tchan",
					    "tchanrt", "rflow";
			bootph-pre-ram;
		};
	};
};

&secure_proxy_main {
	bootph-pre-ram;
};

&dmsc {
	bootph-pre-ram;
	k3_sysreset: sysreset-controller {
		compatible = "ti,sci-sysreset";
		bootph-pre-ram;
	};
};

&k3_pds {
	bootph-pre-ram;
};

&k3_clks {
	bootph-pre-ram;
};

&k3_reset {
	bootph-pre-ram;
};

&wkup_pmx0 {
	bootph-pre-ram;
};

&main_pmx0 {
	bootph-pre-ram;
};

&main_uart0 {
	bootph-pre-ram;
};

&mcu_uart0 {
	bootph-pre-ram;
};

&main_sdhci0 {
	bootph-pre-ram;
};

&main_sdhci1 {
	bootph-pre-ram;
};

&wkup_i2c0 {
	bootph-pre-ram;
};

&main_usbss0_pins_default {
	bootph-pre-ram;
};

&usbss0 {
	bootph-pre-ram;
};

&usb0 {
        dr_mode = "host";
        phy-names = "cdns3,usb3-phy";
	bootph-pre-ram;
};

&fss {
	bootph-pre-ram;
};

&wkup_gpio0 {
	bootph-pre-ram;
};

&serdes_ln_ctrl {
	u-boot,mux-autoprobe;
};

&usb_serdes_mux {
	u-boot,mux-autoprobe;
};

&serdes0 {
	bootph-pre-ram;
};

&main_r5fss0 {
	ti,cluster-mode = <0>;
};

Regards,

Nikhil K

0 Nikhil k 2 months ago in reply to Tanmay Patil

Intellectual 260 points

Hi Tanmay,

Any update on this case?

Regards,

Nikhil K

0 Tanmay Patil 2 months ago in reply to Nikhil k

TI__Mastermind 30450 points

Hi Nikhil,

Sorry for the delayed response.

Can you dump the following register:

0x05060404
0x05060408
0x0506040C
0x05060480
0x05060484
0x05060488
0x0506048C
0x050604C0
0x050604C4
0x050604C8
0x050604CC
0x05060500
0x05060504
0x05060508
0x0506050C
0x05060540
0x05060544
0x05060548
0x0506054C
0x0506E000

Also, is that same USB working on linux kernel.

Regards,
Tanmay

Processors

Processors forum

DRA821U-Q1: Serdes support in uboot