• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 101 subscribers
  • Views 294 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VH-Q1: DMTimer maximum frequency clarification

jars121
Intellectual 635 points

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi TI,

I'm looking to use a DMTimer to provide synchronisation between the TDA4VH and a remote device elsewhere on the board using the EXT_REFCLK1 DMTimer clock source.

Section 6.10.5.22.1 Timing Requirements for Timers in the datasheet has the following table:

In the TRM, Table 5-35 Clock Mapping has the following (using MAIN_TIMER_0 as an example):

Are you able to clarify which of the available MAIN_TIMER_x clock sources is the fastest? I'm trying to determine the maximum DMTimer (either MAIN or MCU) frequency I can use to generate a 32-bit free running up counter.

Thanks!

  • 0
    TI__Mastermind 22680 points

    Hi,

    I have assigned your query to the appropriate engineer, thank you for your patience.
    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Intellectual 635 points

    Thank you Neehar, I appreciate your assistance.

    In the meantime, I've researched this topic further and found the following.

    Table 5-35 above shows that the MAIN_PLLs are selectable function clock sources for the MAIN_TIMER_X instances. The 'J784S4 PLL Defaults' section of the TISCI documentation states a 1GHz default clock frequency for the 'MAIN' PLL (PLLFRACF2_SSMOD_16FFT_MAIN_0):

    From Table 5-35, MAIN_PLL_0.HSDIV OUT8_CLK is an available functional clock source for MAIN_TIMER_0. Using the TISCI default PLL table above, does this correspond then with a 250MHz clock? I.e. 1GHz MAIN PLL CLKOUT with an HSDIV8 value of 4.

    If the above is true, and the other MAIN_PLL_x.HSDIV OUTy_CLK options for the MAIN/MCU_TIMER_x instances can be determined in the same fashion, can I set the MAIN PLL to 2GHz and HSDIV8 to 1 to achieve a 2GHz MAIN_PLL_0.HSDIV OUT8_CLK functional clock for MAIN_TIMER_0? Using the Section 6.10.5.22.1 Timing Requirements for Timers equation above, this would then allow for a timer input period of 9ns or 111MHz?

    My aim is to use a 100MHz LVCMOS input into EXT_REFCLK1 (the maximum input frequency permitted for EXT_REFCLK1 per Table 5-36 in the TRM) as the source for the 32-bit up counter.