Other Parts Discussed in Thread: SK-AM62B-P1
Tool/software:
We are designing the layout of the board on which AM623 and DDR4 will be mounted and performing SI analysis between DDR4 and controller.
The maximum slew rate of the DQ signal during read operation is not within the JDEC standard value.
We have confirmed with the DDR4 manufacturer that this is not a problem as long as the controllers on the receiving side can receive the signals correctly.
【System conditions】
CPU ：AM623 (Speed Grade: T, VDD_CORE: 0.85V)
DDR4 ：Micron (similar series product as SK-AM62B-P1)
Topology ： CPU<-->DDR4 (1 to 1)
・DQ signal is connected to each device by Pin-Pin. (There are no passive components between them.)
・The wiring length of DQ signal is approx. 22mm (upper 8 bits) and approx. 25mm (lower 8 bits).
【Problem】
The maximum slew rate is not within the DDR4 specification.
The maximum slew rate should be 9V/ns or less, but it is approximately 10 to 12V/ns.
【Questions】
・Is there an input slew rate specification for DDR4? (Not mentioned in the datasheet)
・Is there any information regarding this problem from the CPU side?
【Appendix】
It may depend on the drive current on the drive side (DDR4) and the ODT setting value on the receiver side（CPU）, but even if the setting is changed, the slew rate will not be within the specified value.
Changing the drive current or ODT setting value could improve the slew rate slightly, but the signal quality of the entire waveform will become worse.
