TDA4VH-Q1: TDA4VH: SERDES0/1/2/4 config SERDES1 XFI and SERDES2 XFI howto config?

Yes,
In fact, we need 8 networks, at least 1 of which is 10G, and the others are 1G or 2.5G
CPSW9G has at least 5 networks, including 1 10G network

1. 1x10G + 7x1G/2.5G  Can be support?  

2. Can this design work properly in CPSW9G?

3. how to config ?

&serdes_ln_ctrl {
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_PCIE1_LANE2>, <J784S4_SERDES0_LANE3_PCIE1_LANE3>,
<J784S4_SERDES1_LANE0_QSGMII_LANE3>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,/*set net 3,4*/
<J784S4_SERDES1_LANE2_IP4_UNUSED>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,  /*by the note below**, when open SERDES2 LANE1, here must disable ?*/
<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,/*set net 5,6*/
<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>; /*set net 1,8*/
};

What is the impact of the following two sentences on the above?

**If QSGMII is used on any SGMII Port 1 thru 4, then SGMII1/2/3/4 cannot be used for Ethernet functionality since all 4 internal CPSW
ports map to the selected QSGMII SERDES port.
**If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW
ports map to the selected QSGMII SERDES port.

thanks
dongzhang

1) Yes, all ports support 1G SGMII. and 1x10G is ok.

QSGMII - Quad SGMII combines 4 SGMII ports (1.25G Baud) to make it a combined 5G Baud. Hence this statement for QSGMII. But 1G/2.5G SGMII is supported on every port.

On SERDES2, is lane2 assigned as XFI I presume? The rest looks good to me.

Thanks，

This is my design， and all networks can be in Switch mode, yes?

&serdes_ln_ctrl {
idle-states =
<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_PCIE1_LANE2>, <J784S4_SERDES0_LANE3_PCIE1_LANE3>,
<J784S4_SERDES1_LANE0_QSGMII_LANE3>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,/*port 3 1G; port 4 1G*/
<J784S4_SERDES1_LANE2_QSGMII_LANE1>, <J784S4_SERDES1_LANE3_QSGMII_LANE2>, /*port 1 1G; port 2 1G,,,,,??? */
<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,/*port 5 1G; port 6 1G*/
<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>; /*port 1 10G; port 2 10G*/
};
So, is there a port conflict?
Can it be remapped?

Can you reassign XFI to SERDES1 (and use port 1 and port 2) and use SERDES2 for 1G SGMII on the other ports?

&serdes_ln_ctrl {
idle-states =
<J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_PCIE1_LANE2>, <J784S4_SERDES0_LANE3_PCIE1_LANE3>,
<J784S4_SERDES1_LANE0_QSGMII_LANE3>, <J784S4_SERDES1_LANE1_QSGMII_LANE4>,/*port 3 1G; port 4 1G*/
<J784S4_SERDES1_LANE2_IP4_UNUSED>, <J784S4_SERDES1_LANE3_IP4_UNUSED>,
<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,/*port 5 1G; port 6 1G*/
<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>,/*port 1 10G; port 2 10G*/
<J784S4_SERDES4_LANE0_IP3_UNUSED>, <J784S4_SERDES4_LANE1_IP3_UNUSED>,
<J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_QSGMII_LANE8>;/*port 7 1G; port 8 1G*/
};

Is it possible to design like this?