TMS320C6672: Length Rule Reference of DDR3

Yonghun Choi

Prodigy 20 points

Part Number: TMS320C6672

Tool/software:

I am a hardware engineer who designs embedded system using DSP.

Recently, I had a question while reviewing the design of DSP and DDR3.

As you know, the length of DDR3 is constrained.

But references in the following documents are different.

1. SPRACL8_KeyStone DDR3 length Rules Template

2. SPRACL8

3. SPRABI1D

Constraint of CK and CK# are different between SPRACL8 Excel file and application note.

In Application note, constraint is ±1 mil.

In Excel file, constraint is ±2 mil.

And there is no constraint on other note SPRABI1D.

What information should I proceed with the design based on?

over 1 year ago

+1 Shankari G over 1 year ago

TI__Mastermind 25535 points

Yonghun Choi

1. Application notes like SPRABI1D, https://www.ti.com/lit/an/sprabi1d/sprabi1d.pdf are common for all the Keystone devices such as C667x series.

2. SPRACL8_KeyStone DDR3 length Rules Template ----> I guess, this is for Keystone- II "TWO" devices. C6672 comes under Keystone - I "One" devices.

3. In Application notes and Excel will give common/generic information about C66x devices.

4. Better to stick with the Datasheet of the particular part ---> Processor Device-C6672 - https://www.ti.com/lit/ds/symlink/tms320c6672.pdf

If in Datasheet, if the constraint is not given, better to follow https://www.ti.com/lit/an/sprabi1d/sprabi1d.pdf

Regards

Shankari G

0 Yonghun Choi over 1 year ago in reply to Shankari G

Prodigy 20 points

Hi.

Thanks to you. I solved the problem well.

I have an additional question.

Table 6-7 in application note sprabl1d, there is maximum write leveling skew example.

Does it mean skew between CK and DQS?

0 Shankari G over 1 year ago in reply to Yonghun Choi

TI__Mastermind 25535 points

Yonghun Choi

Looping in Kyle to answer this question.

Regards

Shankari G

0 kcastille over 1 year ago in reply to Shankari G

TI__Guru 54797 points

Hello,

Section 6.3.1.9 says ...

"The command delay is defined as delay for the clock, command, control, and address group signals from the DSP to a given SDRAM. The data delay is the delay for the data group signals to that same SDRAM. The write-leveling result is effectively the difference, or skew, between these two delays.

The maximum write-leveling skew is the largest difference between the two delays in the topology to a single SDRAM. Likewise, the minimum write-leveling skew is the smallest difference between the two delays in the topology to a single SDRAM."

Regards,

Kyle

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TMS320C6672: Length Rule Reference of DDR3