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AM6412: Issues when reading from quad flash.

Part Number: AM6412

Tool/software:

Hi all,

We are working on a hardware platform with a TI AM6412 SOC. We boot our firmware/software from a quad flash (macronix,mx25u51245g), which is connected to the OPSI interface.

The corresponding device tree entry is:

flash@0 {
        compatible = "macronix,mx25u51245g", "jedec,spi-nor";
        reg = <0x0>;
        spi-tx-bus-width = <4>;
        spi-rx-bus-width = <4>;
        spi-max-frequency = <108000000>;
        cdns,tshsl-ns = <30>;
        cdns,tsd2d-ns = <3>;
        cdns,tchsh-ns = <3>;
        cdns,tslch-ns = <3>;
        cdns,read-delay = <3>;
        #address-cells = <1>;
        #size-cells = <1>;


The operating system, consisting of the Linux kernel and an initramfs (minimal rootfs, busybox), is loaded by U-Boot and then executed.

We are currently using the TI Kernel 6.1.83-rt28-ti-rt-g96b0ebd82722 from the latest meta-ti Yocto layer.

When we use busybox's flashcp to write arbitrary binary data of arbitrary size (e.g. /dev/random) to a 256k mtd partition, we face two problems:

  1. Data blobs smaller than 9 bytes are written properly to the flash, but the verification read in flashcp fails. We tried to debug the problem
    and ended up in the Linux kernel in drivers/spi/spi-cadence-quadspi.c, function cqspi_mem_process. Applying the patch

    diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
    index b3f5a4e3577d..58247a9733ce 100644
    --- a/drivers/spi/spi-cadence-quadspi.c
    +++ b/drivers/spi/spi-cadence-quadspi.c
    @@ -2151,11 +2151,20 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
     	 * Performing reads in DAC mode forces to read minimum 4 bytes
     	 * which is unsupported on some flash devices during register
     	 * reads, prefer STIG mode for such small reads.
    +	 * 
    +	 * X 
    +	 * X
    +	 * X
    +	 * X
    +	 * 
    +	 * X
    +	 * X
     	 */
    -		if (!op->addr.nbytes ||
    -		    op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
    +		if (!op->addr.nbytes) { //} ||
    +		    //op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
     			return cqspi_command_read(f_pdata, op);
    -
    +		}
    +		
     		return cqspi_read(f_pdata, op);
     	}
     


    as "workaround" seems to fix the issue.

  2. When writing two data blobs with flashcp one after the other, the verification of the second blob fails.

    Example:
    dd if=/dev/random of=/tmp/data1 bs=1 count=192 && dd if=/dev/random of=/tmp/data2 bs=1 count=1872
    flashcp -v /tmp/data1 /dev/mtd8 && flashcp -v /tmp/data2 /dev/mtd8

    Adding debugging messages to flashcp shows, that starting at byte 192, 32 bytes with value 0 (wrong!) are read. From byte 223 the read values
    are correct again. Further debugging ended up again in the Linux kernel in drivers/spi/spi-cadence-quadspi.c, now function cqspi_direct_read_execute.
    Applying the patch

    diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
    index 58247a9733ce..e6fdbabea8a6 100644
    --- a/drivers/spi/spi-cadence-quadspi.c
    +++ b/drivers/spi/spi-cadence-quadspi.c
    @@ -2063,10 +2063,11 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
     	u_char *buf = op->data.buf.in;
     	int ret;
     
    -	if (!cqspi->rx_chan || !virt_addr_valid(buf) || len <= 16) {
    +	/* Workaround for read problems from userspace (e.g. flashcp verification) */
    +	//if (!cqspi->rx_chan || !virt_addr_valid(buf) || len <= 16) {
     		cqspi_memcpy_fromio(op, buf, cqspi->ahb_base + from, len);
     		return 0;
    -	}
    +	//}
     
     	if (!cqspi_use_phy(f_pdata, op))
     		return cqspi_direct_read_dma(f_pdata, buf, from, len);


    seems to "workaround" the problem.

The fixes for both problems are in the best case a workaround, but do not solve the problem itself.

Has anybody an idea, what the root cause is?

  • Hi,

    The subject matter expert is out of office, please expect delay in responses.

    Regards,
    Krunal

  • Hi Krunal,

    Thanks for letting me know.

    Regards,

    Ingo

  • Hi Ingo,

    can you measure/verify the actual QSPI clock frequency using a scope during transfers?

    Your device tree file is trying to set it to spi-max-frequency = <108000000>; which is not a valid configuration. Without using "PHY mode" you are limited to "TAP mode" which means max. speed is 25MHz DDR or 50MHz SDR (same effective throughput). Note that with SDK v9.x's Kernel v6.1x the use of "PHY mode" is not supported yet.

    Regards, Andreas

  • Hi Andreas,

    We verified the clock back in the day when we were using kernel 5.10. It was 166 / 2 MHz. If I understood the TRM right, this is the maximum frequency to expect.

    But when you say, that the phy mode is not supported yet, I will try to lower the frequency. Will the phy mode ever be supported in 6.1?

    Thanks,

    Ingo

  • HI Ingo,

    We verified the clock back in the day when we were using kernel 5.10. It was 166 / 2 MHz.

    Ok that's definitely too fast. Try lowering the frequency to 50MHz and see if this solves your read issues. It should work without "hacking" the driver code (which likely makes things work only by chance, as you are changing the transfer timings around, to a slower mode).

    There's no plan to support QSPI PHY mode on current SDK v9.1 / Kernel v6.1, although there are some preliminary patches available.

    I need to double check but I think the plan is to officially support this for the upcoming SDK v10.x series (using Kernel v6.6), which is about a week a way from release. Let me check and get back here soon.

    Regards, Andreas

  • Hi Andreas,

    I did some additional tetsing and verification.

    • When I set a frequency of 108 MHz in the DT, we can measure an output frequency of 83 MHz (166.6/2), as more or less expected.
    • When I set a frequency of 50 MHz in the DT, we can measure an output frequency of 41 MHz (166.6/4), as expected.
    • When I set a frequency of 25 MHz in the DT, we can measure an output frequency of 20 MHz (166.6/8), as expected.

    In all cases the flash is detected (read delay adjusted properly) BUT the 2 problems remain. So, I fear it's not just a matter of clock speed. And moreover, my second patch disables DMA reads, but the measured performance of flashcp in the user space is the same and running flashcp-tests in a loop (up to 2000 iterations) works without error.

    Best, Ingo

  • Hi Ingo,

    Good inputs, thanks for the testing. Which AM64x silicon revision are you using? SR1.0? SR2.0?

    Regards, Andreas

  • Hi Andreas,

    We are on SR2.0.

    Regards, Ingo

  • Ingo,

    great, thanks for confirming. 

    I need to double check but I think the plan is to officially support this for the upcoming SDK v10.x series (using Kernel v6.6), which is about a week a way from release. Let me check and get back here soon.

    Actually SDK v10.0 has just hit the web. Before embarking on some lengthy debug/analysis effort here, can you please try the Kernel from SDK v10.0 to see if this has any impact on your QSPI behavior?

    SDK Download Location: https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-AM64X/10.00.07.04

    SDK Kernel Direct Link: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/?h=10.00.07&id=6de6e418c80edfbe08f4a5f851c721bd60c0123b

    As for QSPI PHY mode support, SDK v10.0 has this enabled/tested for QSPI NAND. My understanding is what you have is a QSPI NOR flash, correct? There's PHY mode base support for this combination in SDK v10.0 too but it looks like some additional minor changes are needed to actually test/use this. The responsible engineer is currently out of the office and will be back next week. I'll contact him at this time to clarify what's needed so we can fully enable/use PHY mode for your scenario.

    However anyways in the meantime the goal should be to get what you have working well, PHY mode is not in the picture for this yet.

    Regards, Andreas

  • Hi Andreas,

    Yes, right, we are using a NOR flash. As soon as the responsible engineer has clarified the additional needs, I will try the new Kernel 6.6 and see if our problems are gone.

    Thanks, Ingo

  • Hi Ingo,

    As soon as the responsible engineer has clarified the additional needs, I will try the new Kernel 6.6 and see if our problems are gone.

    just to make sure we are on the same page here; you can try Kernel 6.6 from SDK v10.0 in a non-PHY mode fashion right away (just like you are using in your current setup today), this part doesn't need any more pieces from the TI side.

    As for QSPI NOR PHY-mode support (next step), I've learned there are some internal/test patches for this. I hope to get my hand on those in the next ~2 days when the responsible engineer comes back to the office to see if this is something you may be able to use because without this you'll be limited to the non-PHY clock speeds (which is 50MHz SDR or 25MHz DDR mode).

    Thanks and Regards,
    Andreas

  • Hi Andreas,

    Thanks for the clarification. I will give it a try as soon as possible.

    Regards, Ingo