• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 515 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EHRPWM and TBCLK

Steve Kreyer
Intellectual 520 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Hi,

 

in the reference guide of the OMAP-L138 it is mentioned that the source for TBCLK is SYSCLKOUT. Since my processor is running @300MHz I thought if the fields HSPCLKDIV and CLKDIV of the TBCTL register are both set to DIVBY1 the frequency of one counter step is 300 MHz.

Now Iam observing the following: If I set the maximum period in TBPRD to 0 I measure a frequency of 75 MHz with the oscilloscope. Can you give me hint why? I expected 300MHz ...

 

Here is my PWM configuration:

    syscfg0_regs->KICK0R = CSL_FMK(SYSCFG_KICK0R_KICK0, 0x83e70b13);
    syscfg0_regs->KICK1R = CSL_FMK(SYSCFG_KICK1R_KICK1, 0x95A4F1E0);
    syscfg0_regs->CFGCHIP1 = CSL_FMKT(SYSCFG_CFGCHIP1_TBCLKSYNC, STOP);
    ehrpwm1_regs->TBCTL = CSL_FMKT(EHRPWM_TBCTL_FREE_SOFT, RUNFREE) |
                          CSL_FMKT(EHRPWM_TBCTL_HSPCLKDIV, DIVBY1) |
                          CSL_FMKT(EHRPWM_TBCTL_CLKDIV, DIVBY1);
    ehrpwm1_regs->TBPRD = CSL_FMK(EHRPWM_TBPRD_TBPRD, 0U);
    ehrpwm1_regs->TBCTL = CSL_FINST(ehrpwm1_regs->TBCTL, EHRPWM_TBCTL_CTRMODE, DOWN);
    ehrpwm1_regs->AQCTLA = CSL_FMKT(EHRPWM_AQCTLA_ZRO, EPWMXATOGGLE);
    syscfg0_regs->CFGCHIP1 = CSL_FMKT(SYSCFG_CFGCHIP1_TBCLKSYNC, ENABLE);

 

Any help would be very appreciated. If you need additional information please let me know.

 

Kind Regards,

Steve

  • 0
    Intellectual 445 points

    Hi Steve,

    The ehrpwm peripheral is connected to SYSCLK2 coming from PLL0 or PLL1 depending upon the ASYNC3_CLKSRC field of CFGCHIP3 register. Kindly refer to Figure 7.1 (Section 7 -  device Clocking) in OMAPL138 System Reference Guide.

    Regards,

    Awais Masood

    Mentor Embedded

    Nucleus | Services | UI | Multi-OS

     

  • 0 in reply to Awais Masood
    Intellectual 520 points

    Hi Awais,

     

    thanks for your answer and sorry the delay. Ok the picture makes it clear. ASYNC3_CLKSRC is set to 0 and according to my PLL configuration  SYSCLK2 should be configured  to be 150 MHz. But still why is the frequency 75 MHz (I thought programming TBPRD to 0 is one step until the programmed action (TOGGLING) is applied to the output)?

     

    Unfortunatly since my input voltage is 1V2 and according to TIs Clocking_Check XLS it is not possible to set SYSCLK2 higher than 150MHz (PLL1) or 187,5 MHz(PLL0). Do you know any other way to achieve a PWM  frequency of 13 MHz for the output EPWM1A? I can only set it to either 15 MHz or the next lower frequency is 12.5 MHz. I think both choices are not exact enough for my application.

     

    Thanks for your help.

     

    Kind Regards,

    Steve