• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 102 subscribers
  • Views 121 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6745: UART1 receiver interruption is not enabled even though I had configed in tcf script of DSP/BIOS

xing long
Prodigy 240 points
Part Number: TMS320C6745

Tool/software:

I need add UART driver code into a very old project which developed with DSP/BIOS v5.42.1.9.At first i used EDMA3 to transfer received data from Rx FIFO of UART1 to data buffer in SRAM,two problem appears,one was that EDMATC0 reported "Read address error" because source address was not right,but i was very sure that i wrote the right source address in  Parameter Set RAM. Another problem is that the transfer completion interruption can not be serviced even though i already configed ISR for it in tcf file like showing in picture 1 .

HWI configuation in tcf

but actually the IE9 is not enabled in core register IER .

BTW,the reason leaded to that EDMATC0 reported "Read address error" ,I guessed,is that the onchip 256k SRAM is working as L2 cache.I just uncheck the L2 Cache box in memory brower showing in picture 2,then EDMA works well.But i can't find a place where i can config the way onchip 256k SRAM working in gconf.exe.

l2 cache

As have no idea to solve the two problem,I give up trying to use EDMA,and just use a UART receiver ISR for storing coming data.As the same problem encountered above,the UART receiver interruption can not be serviced.

I want to know how to config the onchip 256k SRAM to work in SRAM not L2 Cache,also why the corresponding bit in IER is not set after configured in gconf.exe

  • 0
    TI__Guru* 86095 points

    Hello,

    Please note that DSP/BIOS code is very old, and we can no longer support questions about it on the forums.

    When I skimmed through the technical reference manual (TRM), it seemed like the internal SRAM was only ever referred to as L2 cache. I am sending your thread over to a member of the hardware apps team to comment.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 240 points

    Thanks for your replying.

    According to literature "TMS320C674x DSP Megamadule Reference Guide"(SPRUFK5A),in response to a global reset,the L2 cache is switched to "All-RAM" mode（Reference to Chapter 4.3.3 Reset Behavior）.

    At now,I care most about that how to enable interruption by gconf.exe.Please let me know if you have any idear,as i have been stalled for a week.

    Best regards

  • +1 in reply to xing long
    Prodigy 240 points

    I have found the reason why interruption was not serviced.it's because DSP/BIOS require user to mannually enable interruption by using fallowing codes:

    #include <c6x.h>

int main()
{
...
IER |= 0x100;///< Enable INT8
...
}

  • 0 in reply to xing long
    TI__Guru**** 153749 points

    Hello Xing Long, 

    Thank you and appreciate adding the observations.

    Regards,

    Sreenivasa