AM6422: Reading on-board EEPROM at 0x51 failed -1

Wendy

Part Number: AM6422

Tool/software:

Hi,

We use our own hardware, using SDK 8.6,AM6422. When the system starts, the following message is printed in uboot, and it is found that it will be restarted several times in uboot and then enter the system。

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

U-Boot SPL 2021.01-g2ee8efd654 (Feb 27 2023 - 13:51:27 +0000)
EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
Resetting on cold boot to workaround ErrataID:i2331
resetting ...

U-Boot SPL 2021.01-g2ee8efd654 (Feb 27 2023 - 13:51:27 +0000)
EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
SPL initial stack usage: 13424 bytes
Trying to boot from MMC1
Authentication passed
Authentication passed
Authentication passed
Authentication passed
init_env from device 9 not supported!
Starting ATF on ARM64 core...

NOTICE: BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
NOTICE: BL31: Built : 13:46:23, Feb 27 2023
I/TC:
I/TC: OP-TEE version: 3.20.0 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Mon Feb 27 13:47:09 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2021.01-g2ee8efd654 (Feb 27 2023 - 13:49:29 +0000)
EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Capybar')
Trying to boot from MMC1
Authentication passed
Authentication passed

U-Boot 2021.01-00001-g7e12ed6f28-dirty (Aug 20 2024 - 09:21:31 +0800)

SoC: AM64X SR2.0 HS-FS
Model: Texas Instruments AM642 EVM
EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
DRAM: 2 GiB
NAND: 0 MiB
MMC: mmc@fa10000: 0, mmc@fa00000: 1
Loading Environment from MMC... OK
In: serial@2800000
Out: serial@2800000
Err: serial@2800000
EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
Net: eth0: ethernet@8000000port@1
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0(part 0) is current device
SD/MMC found on device 0
Failed to load 'boot.scr'
** Unrecognized filesystem type **
19147264 bytes read in 95 ms (192.2 MiB/s)
39808 bytes read in 3 ms (12.7 MiB/s)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 000000008fef3000, end 000000008fffffff ... OK

Starting kernel ...

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

I hope you can help analyze it，and thank you!

over 2 years ago

0 Aparna Patra over 2 years ago

TI__Genius 12980 points

Hello,

This looks like a known error noted as an errata:

A MAIN domain POR occurs using the hardware MCU_PORz signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or

CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor and internal bus structures may get into a state

which is only recoverable with full device reset using MCU_PORz.

Please refer: https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/mach-k3/am642_init.c?h=08.06.00.007#n259

Regards,

Aparna

0 Wendy over 2 years ago in reply to Aparna Patra

Intellectual 900 points

Hello，

I compared my code with yours and found that they are the same. Our hardware has CPLD, and the CPU reset is directly connected to the CPLD. When powered on, the CPLD controls the reset pin. Is this part not matched well?Can you tell me the reset sequence in detail? For example, MAIN domain POR, MCU_PORz, CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR.

And also print "EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1"message,how would i modify?

0 Aparna Patra over 2 years ago in reply to Wendy

TI__Genius 12980 points

Hi, I have forwarded the query to an expert to comment about the reset sequence involving the above issue. Expect reply in a few hours.

Regards,
Aparna

0 Swargam Anil over 2 years ago in reply to Aparna Patra

TI__Guru 55608 points

Hello,

In the MCU+SDK and Processor SDK there is Workaround for reading CPSW registers after the POR.

When SOC receives POR, either it is from HW (MCU_PORz) or SW (CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR), then SBL and u - boot checks the POR status, If device went through the POR , then again SBL or U boot does the Warm Reset the SOC.

This is WA for reading CPSW registers after the POR.

Wendy said:
Our hardware has CPLD, and the CPU reset is directly connected to the CPLD. When powered on, the CPLD controls the reset pin. Is this part not matched well?

If CPLD controls the POR pin , then your board will get reset two times due to CPSW WA.

Wendy said:
And also print "EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1"message,how would i modify?

Aparna Patra, can you please help here ?

Regards,

Anil.

0 Wendy over 2 years ago in reply to Aparna Patra

Intellectual 900 points

Hi,

I followed the link and recompiled uboot,copy the uboot.img file,it also have the print"EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1"message,how would i modify?"

e2e.ti.com/.../4729933