We are having issues with I2C on our DM3730 platform, which is somehow related to clocks.
With original u-boot settings, we were only getting 400MHz top speed. With the EVM 3730 running the latest Windows CE download from the TI Website (May 2011 version), we were seeing 1000MHz.
So we modified our u-boot to use the same clocks as Windows CE. However, when we did so, I2C started having random timeouts, where everything seemed normal, but then writing a "Read" transaction to the bus would just never go to the bus. I2C signals on the bus are clean, at the right frequency (100kHz), and the same in both cases regardless of processor clock. The udelay() function timer was updated accordingly, so that udelay(x) is in fact x microseconds, and this was verified on a logic analyzer.
Making the following changes to match what EVM w/ WinCE is doing, and it is enough to cause I2C to start having errors:
clksrc_ctrl divider set to 1 instead of 2
clksel1_pll_mpu M=500, N=12, M2=1
We are using CTT (Clock Tree Tool) and found a few potential issues.
On the EVM 3730 using the latest software downloaded from TI Website (May 2011) , DPLL4 appears to be wrong. For example, CTT says PRM_192M_ALWON_CLK is 96MHz; shouldn't that be 192MHz?
For the CORE_96M_FCLK, CTT indicates that CLKSEL1_PLL Bit 6 is set to 1 for 96MHz, and 0 for CM_SYS_CLK. However, DM3730 TRM says that bit is 0 for 96MHz, and 1 for SYS_CLK. Which is correct?
We also noticed that the I2C driver in WinCE had retries. That seemed strange; why should we need retries unless the I2C connections are unreliable? Sure enough, removing them causes timeouts similar to what we are seeing in U-boot. It seems like that might have been a workaround, and fixed the wrong problem, when the real problem could be related to clocks?
So the question is, given a 26MHz crystal, and a Rev 1.2 DM3730 that is rated for 1GHz operation, and attempting to run in a maximum performance scenario, what would be the correct values for all the clocks in the system. Alternately, can you provide CTT register dump of an ideal target clock setup?
Here is the CTT Dump when running EVM with Windows CE; the dump is printed at the end of OEMInit().
DeviceName OMAP3630_ES1.x
0x48002274 0x05000000
0x480022d8 0x01000000
0x48004000 0x00000000
0x48004004 0x00000007
0x48004040 0x0011900c
0x48004044 0x00000001
0x48004904 0x00000277
0x48004940 0x0011f40c
0x48004944 0x00000001
0x48004a00 0x00000000
0x48004a08 0x00000000
0x48004a10 0x00000042
0x48004a18 0x00000000
0x48004a30 0x7ffffed1
0x48004a38 0x00000004
0x48004a40 0x0000130a
0x48004b00 0x00000000
0x48004b10 0x00000000
0x48004b40 0x00000000
0x48004c00 0x00000029
0x48004c10 0x0000002d
0x48004c30 0x0000003f
0x48004c40 0x00000014
0x48004d00 0x00770007
0x48004d04 0x00000007
0x48004d40 0x08c80c00
0x48004d44 0x0481b00c
0x48004d48 0x00000009
0x48004d4c 0x0000780c
0x48004d50 0x00000001
0x48004d70 0x00000003
0x48004e00 0x00000003
0x48004e10 0x00000001
0x48004e30 0x00000001
0x48004e40 0x00001009
0x48004f00 0x00000000
0x48004f10 0x00000000
0x48004f30 0x00000001
0x48004f40 0x00000004
0x48005000 0x0003e808
0x48005010 0x0003e808
0x48005400 0x00000000
0x48005410 0x00000000
0x48005430 0x00000001
0x48306ae0 0x000f0307
0x48306d70 0x00000080
0x48307270 0x00000050
0x483074e0 0x00030107
Alternately, if this is already documented somewhere, please point me to it. There are hints in various documents, like the datasheet and TRM, as to what the frequencies should be, but there isn't a single table that we can use to compare CTT results of our system to an 'ideal' system, and in most cases the options are provided, but no guidelines as to which values to use when. For example, Table 4-24 in DM3730 datasheet, Graphic Accelerator Clocks, shows 3 different maximum frequencies, yet provides no guidelines on which ones we should be getting. If the answer is the left-most column, then the DPLL4 clock, and values derived from DPLL4, do not match the values we see in CTT for the EVM w/ WinCE.
Thanks,
Dave