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TMS320DM365 (DMVA2) .IBIS model

Elvis Mota
Prodigy 200 points
Other Parts Discussed in Thread: TMS320DM368

Hi,

I'm using Hyperlynx to simulate the DDR2 interface of my design using DMVA2. I downloaded the .ibis model file for the TMS320DM368. Could you confirm this is the appropriate model for the DMVA2 part?

Also, when selecting a model for drivers in the DDR controller module, there are basically four options for 1.8V logic.

NOSR0_NOTERM_1P8  Cell operated at 1.8(nom)
|NOSR0_NOTERM_1P8
|BUFFER OPERATING AT FAST MODE WITH 1.8V SUPPLY WITH +/-10% VARIATION

SR0_NOTERM_1P8  Cell operated at 1.8(nom)
|SR0_NOTERM_1P8
|BUFFER OPERATING AT SLOW MODE WITH 1.8V SUPPLY WITH +/-10% VARIATION

NOSR0_NOTERM_0.1_1P8  Cell operated at 1.8(nom)
|NOSR0_NOTERM_0.1_1P8
|BUFFER OPERATING AT FAST MODE WITH 1.8V SUPPLY WITH +/-0.1V VARIATION

SR0_NOTERM_0.1_1P8  Cell operated at 1.8(nom)
|SR0_NOTERM_0.1_1P8
|BUFFER OPERATING AT SLOW MODE WITH 1.8V SUPPLY WITH +/-0.1V VARIATION

Since I'm relatively new to simulations using IBIS models, I would like to understand the differences between SR0 vs NOSR0, and also the differences between FAST and SLOW modes.

I want to understand how these options can affect my simulation.

 

Regards,

 

Elvis

  • 0
    TI__Prodigy 480 points

    Elvis,

    If I may ask, what is your goal in simulating the DDR2 bus?  TI does not recommend using IBIS simulations to model signal integrity on a DDR2 bus.  Instead we have created a very specific layout requirement which will work correctly if followed completely.  Details of the reasoning for this decision are described here: http://www.ti.com/litv/pdf/spraav0a.  The DDR2 layout requirement is included in the device data sheet.

    Regards,

    -phil

  • 0 in reply to Philip Baltz
    Prodigy 200 points

    Hi Phil,

    The goal in using Hyperlynx to simulate the DDR2 bus is to have another method of verifying the integrity of the bus at its maximum speed.

    I do agree that simulation results are dependent on how well the simulation is set up. However, it is a very good indication of what to expect assuming that models being used are as close to the actual devices as they can be.

    Due to design constrains, not all of the requirements listed in the device datasheet could be followed strictly. So, simulation is a method for me to evaluate if I should expect any problem due to the artwork before having boards fabricated.

    In any case, in my original question I was trying to understand in more detail the corner cases used in the model provided for the DM368 drivers.

    Regards,

     

    Elvis

  • 0 in reply to Elvis Mota
    TI__Expert 4510 points

    Hi Elvis,

     

    Can you please comment on requirements that you can not follow from device datasheet? For DDR specific portion, our recommendation is to use canned schematics as per hardware design guide document below -

    http://processors.wiki.ti.com/index.php/DM36x_Hardware_Design_Guide

    I am still checking on corner cases used in IBIS model.

    Thanks,

    Prateek

     

  • 0 in reply to Prateek Bansal
    Prodigy 200 points

    Hi Prateek,

     

    The requirements that cannot be followed entirely are the center-to-center minimum distance between one net class to another and the DQ/DQS Skew length mismatch (segment between DDR2 controller and termination).

    I'm trying to validate my simulation by measuring the SI in a current design and comparing to the simulator results.

     

    Regards,

     

    Elvis

  • 0
    TI__Prodigy 480 points

    Elvis,

    The difference between SLOW and FAST are described in the table below.

    Setting

    Comments

    NOSR0

    FAST mode

    SR0

    SLOW mode which is roughly 33% slower than FAST mode

    Rgeards,

    -phil

  • 0 in reply to Philip Baltz
    Prodigy 10 points

    Hi,

    How can I config the DM368 to work on NOSR0/SR0/FAST/SLOW?

    Witch registers control on this option?

    Regards,

    Matan