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DDR3 Initialization

KENJI SASAKI
Prodigy 70 points


I am currently writing DDR 3 initializaition program for C6A8168 in C.

 

In order to proceed with this, I used the CCSv4 GEL file to determine necessary initialization parameters, however, the program I wrote in the NOR Flash  (using the same parameters as the GEL file) always gets stuck during the  DDR3 boot process, returning EXCEPTION error. 

To be more precise, the boot process hangs during the initialization of SDRRCR(SDRAM Refresh Control Register) even I am following the steps as described in the GEL program.  The program comes to a halt right after the following process #2.

 

#1. SDRRCR = 0x0000613B

#2. SDRRCR = 0x1000613B

#3. SDRRCR = 0x10000000 + 0x1841

 

On the other hand, a different description is provided in your TRM, which goes:

 

1. SDRRCR = 0x80000000 + 0x1841

2. SDRRCR = 0x90000000 + 0x1841

3. SDRRCR = 0x10000000 + 0x1841

 

The above does go through without returning any error, however, DDR is NOT initialized and remains all "0".

 

Could you provide me with a workaround on this issue?

 

Thanks, and best regards.

Ken

  • 0
    TI__Prodigy 370 points

    Hi,

    On Which silicon version DDR3 initialization tried? Can you please get the value of 0x48140600? DDR3 is supported from 1.1 Silicon version.

     

    Regards,

    Keshava

  • 0 in reply to xkeshavm
    Prodigy 70 points

    Hi,

    We may be using 1.1 Silicon version.

    The value of 0x48140600 is   0x1B81E02F.

    Is this the 1.1 Silicon ?

    Regrads,

    Ken

  • 0 in reply to KENJI SASAKI
    TI__Prodigy 370 points

    Hi Ken,

     

      The last nibble is 1(0x1B81E02F), it is 1.1 silicon version.

    Can you please provide data on the below questons?

    1. Is the initialization fails for EMIF0 or EMIF1 or both?

    2. Is the DDR3 controller values changed to targetted memory part in the gel or linux code?

    3. Is the DDR3 PHY Slave ratio values for your board calculated based on the app note procedure documented ?

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    4. Did you try to bring up DDR3 with CCS using gel file?

    Correct value to be programmed in the REFRESH field to meet the typical DDR3 device specified delay time of 500us between the deassertion of reset and the assertion of CKE as part of the initialization sequence. Thats the reasony why we start with higher refresh rate and then change the refresh rate based on the targetted freqeuncy.

     

     

     

    Regards,

    Keshava

     

     

     

  • 0 in reply to xkeshavm
    Prodigy 70 points

    Hi Keshava,

    The answers for your question are belows..

    1. Both EMIF0 and EMIF1 are fails.

    2. Yes, our board is using 16bit DDR3 devices and placed parallel 32bit mode.

    3. Slave Ratios are calculated by our original program. (Seed values are calculated by Excel sheet which provided by TI.)

        We could not find Ratio values with the process below. 

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    4. Yes. It's no problem when using GEL file. DDR3 are clearly accessible.

     

    Regards, 

    Ken

     

    xkeshavm said:

    Can you please provide data on the below questons?

    1. Is the initialization fails for EMIF0 or EMIF1 or both?

    2. Is the DDR3 controller values changed to targetted memory part in the gel or linux code?

    3. Is the DDR3 PHY Slave ratio values for your board calculated based on the app note procedure documented ?

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init

    4. Did you try to bring up DDR3 with CCS using gel file?

    Correct value to be programmed in the REFRESH field to meet the typical DDR3 device specified delay time of 500us between the deassertion of reset and the assertion of CKE as part of the initialization sequence. Thats the reasony why we start with higher refresh rate and then change the refresh rate based on the targetted freqeuncy.

     

    Regards,

    Keshava

     

  • 0 in reply to xkeshavm
    TI__Prodigy 370 points

    Hi Ken,

      Thanks for confirming DDR accessing working through gel file.

    On 3, the app note clearly documents, how to use the calculated seed value from excel sheet and key in the seed values to CCS based program DDR3_slave_ratio_search.out . You didnt find the procedure.

    May be some sequence is missing in the uboot code. 

     

    Regards,

    Keshava