I have configured McBSP0 using internal clock in DLB mode with FSX generation on every DXR to XSR copy. I can see that 1st data is copied to DXR, but it is not recieved at DRR. The RRDY bit is not getting enabled. Hence code is getting stuck at that condition check of RRDY. What could be the reason that RRDY is not getting enabled, when i see that data is being transmitted.
The code is as given below:
void McBSP_initDLB(McBSP_reg *McBSP)
{while(McBSP->SPCR & 0x00C00000);
McBSP->SPCR = 0x0000;
McBSP->SPCR |= (0x1 << 15) ;
McBSP->PCR |=(0x1<<11)|(0x1<<9)|(0x0<<8)|(0x1<<10); / / FSXM=1,FSRM=1,CLKXM=CLKRM=1
McBSP->SRGR =(0x0<<28); // FSGM =0
McBSP->XCR = 0x040;
McBSP->RCR = 0x040;
while(McBSP->SPCR & 0x00C00000); // Ensure GRST = FRST = 0
while(McBSP->SPCR & 0x00010001); // Ensure RRST = XRST = 0
wait(2*100);
McBSP->SRGR |=(0x1<<29); //CLKSM 1-> McBSP internal clock
McBSP->PCR &= (~0x80); // SCLKME = 0
McBSP->SPCR |= (0x1<<22); //set GRST=1
wait(2*100);
McBSP->SPCR |= (0x1<<16); // XRST =1
wait(2*100); // Wait for 2 CLKG cycles
McBSP->SPCR &= ~(0x1<<16); //XRST =0 to clear XSYNCERR that might have occur
McBSP->SPCR |=0x00010001; // XRST = RRST = 1
}
//Function to transmit
void write(signed short int data1,McBSP_reg *Port)
{
while(!(Port->SPCR & (0x1<<17))); // Wait until transmitter is ready for new data in DXR(XRDY=1)
Port->DXR = data1;
}
//Function to recieve
void read()
{
while(!((McBSP0->SPCR)& 0x2)); //Ensure RRDY =1. Data is ready to be read from DRR
data = McBSP0->DRR;
}
The code is getting stuck at the line highlighted.
Please suggest a solution to this.
Regards,
Poornima Tom
