• State TI Thinks Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 475 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4AEN-Q1: CAN support

Vincent Wan
Intellectual 450 points
Part Number: TDA4AEN-Q1

Tool/software:

We are using SDK 9.2 for the TDA4AEN and CAN seems to be disabled:

root@j722s-evm:~# ip link set can0 up type can bitrate 500000
Cannot find device "can0"

What is the way to enable CAN functionality on this platform?

  • 0
    TI__Guru 51503 points

    Hi Vincent,

    Can you send the output from:

    • ifconfig -a

    This lists out the name for all CAN interfaces regardless of them being active. If that command does not list out any CAN interfaces, then most likely they are not defined in device tree.

    This commit adds the CAN interface to the device tree for TDA4AEN which you can add to your device tree: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/arch/arm64/boot/dts/ti/k3-j722s-evm.dts?h=ti-linux-6.6.y&id=33665a21aeb826b802f1bc108acc2e27a3f07472

    Alternatively, SDK 10.0 should have this patch integrated so you can download the prebuilt SD card image for SDK 10.0 TDA4AEN to evaluate CAN.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Intellectual 450 points

    Thanks Takuma, the output does not list any CAN interfaces:

            root@j722s-evm:~# ifconfig -a
        eth0: flags=4099<UP,BROADCAST,MULTICAST>  mtu 1500
                ether ca:f0:5c:01:04:10  txqueuelen 1000  (Ethernet)
                RX packets 0  bytes 0 (0.0 B)
                RX errors 0  dropped 0  overruns 0  frame 0
                TX packets 0  bytes 0 (0.0 B)
                TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

        lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
                inet 127.0.0.1  netmask 255.0.0.0
                inet6 ::1  prefixlen 128  scopeid 0x10<host>
                loop  txqueuelen 1000  (Local Loopback)
                RX packets 93  bytes 7707 (7.5 KiB)
                RX errors 0  dropped 0  overruns 0  frame 0
                TX packets 93  bytes 7707 (7.5 KiB)
                TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

    After modifying the dts file, what should I do for the changes to take effect?

    Thanks,

    Vincent

  • 0 in reply to Vincent Wan
    TI__Guru 51503 points

    Hi Vincent,

    After applying the patch to dts file, you would need to build the dts file into a dtb file, then copy the generated dtb file onto the SD card.

    Following the userguide here should allow you to build and flash the device tree: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/10_00_00_08/exports/docs/linux/Overview_Top_Level_Makefile.html

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Intellectual 450 points

    Hi Takuma,

    Thank you for your guidance. I have made some progress. After updating the dtb file, I can now communicate over mcu_mcan0, but not mcu_mcan1. The latter seems to be recognized though:

    root@j722s-evm:~# ip link set mcu_mcan1 up type can bitrate 500000
[   19.602801] IPv6: ADDRCONF(NETDEV_CHANGE): mcu_mcan1: link becomes ready
root@j722s-evm:~# cansend mcu_mcan1 345#1122334455667788
[   28.593583] can: controller area network core
[   28.598042] NET: Registered PF_CAN protocol family
[   28.609162] can: raw protocol
root@j722s-evm:~# [   28.614142] m_can_platform 4e18000.can mcu_mcan1: bus-off

    I have attached my updated dts file. Is there anything I may have been doing incorrectly?

    Best regards,

    Vincent

    Fullscreen 6708.k3-j722s-evm.dts.txt Download 
    // SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for the J722S-EVM
 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Schematics: https://www.ti.com/lit/zip/sprr495
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include "k3-j722s.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>

/ {
	compatible = "ti,j722s-evm", "ti,j722s";
	model = "Texas Instruments J722S EVM";

	aliases {
		serial0 = &wkup_uart0;
		serial2 = &main_uart0;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		usb0 = &usb0;
		usb1 = &usb1;
	};

	chosen {
		stdout-path = &main_uart0;
	};

	memory@80000000 {
		/* 8G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
		      <0x00000008 0x80000000 0x00000001 0x80000000>;
		device_type = "memory";
		bootph-pre-ram;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global cma region */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x38000000>;
			linux,cma-default;
		};

		secure_tfa_ddr: tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			no-map;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>;
			no-map;
		};

		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		c7x_0_memory_region: c7x-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
		};

		c7x_1_memory_region: c7x-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a5000000 {
			reg = <0x00 0xa5000000 0x00 0x1c00000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	vmain_pd: regulator-0 {
		/* TPS65988 PD CONTROLLER OUTPUT */
		compatible = "regulator-fixed";
		regulator-name = "vmain_pd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
		bootph-all;
	};

	vsys_5v0: regulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: regulator-mmc1 {
		/* TPS22918DBVR */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
		bootph-all;
	};

	vdd_sd_dv: regulator-TLV71033 {
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	vsys_io_1v8: regulator-vsys-io-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_io_1v2: regulator-vsys-io-1v2 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&led_pins_default>;

		led-0 {
			label = "j722s-evm:red:heartbeat";
			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
			function = LED_FUNCTION_HEARTBEAT;
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			label = "j722s-evm:green:disk-activity";
			gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
			function = LED_FUNCTION_DISK_ACTIVITY;
			linux,default-trigger = "mmc1";
			default-state = "off";
		};
	};

	hdmi0: connector-hdmi {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "a";
		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&sii9022_out>;
			};
		};
	};

	transceiver0: can-phy0 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&mcu_gpio0 12 GPIO_ACTIVE_HIGH>;
	};

	transceiver1: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};

	transceiver2: can-phy2 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>;
	};
};

&main_pmx0 {

	/delete-property/ interrupts;
	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
			J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
		>;
		bootph-all;
	};

	main_i2c1_pins_default: main-i2c1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */
			J722S_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A22) I2C1_SDA */
		>;
		bootph-all;
	};

	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x01c8, PIN_INPUT, 0)	/* (F19) UART0_RXD */
			J722S_IOPAD(0x01cc, PIN_OUTPUT, 0)	/* (F20) UART0_TXD */
			J722S_IOPAD(0x01d4, PIN_OUTPUT, 0)	/* (B21) UART0_RTSn */
			J722S_IOPAD(0x01d0, PIN_INPUT, 0)	/* (E22) UART0_CTSn */
		>;
		bootph-all;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
		>;
		bootph-all;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
			J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
			J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
			J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
			J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
			J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
			J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */
		>;
		bootph-all;
	};

	ospi0_pins_default: ospi0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */
			J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */
			J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */
			J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */
			J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */
			J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */
			J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */
			J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */
			J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */
			J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */
			J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */
		>;
		bootph-all;
	};

	main_i2c2_pins_default: main-i2c2-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */
			J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */
		>;
	};

	mdio_pins_default: mdio-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
			J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
		>;
	};

	rgmii1_pins_default: rgmii1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */
			J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */
			J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */
			J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */
			J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */
			J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */
			J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */
			J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */
			J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */
			J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
			J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
		>;
	};

	led_pins_default: led-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0244, PIN_INPUT, 7) /* (A24) MMC1_SDWP */
		>;
	};

	main_usb1_pins_default: main-usb1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
		>;
	};

	main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0110, PIN_INPUT, 7) /* (G27) MMC2_DAT1.GPIO0_67 */
		>;
	};

	main_dpi_pins_default: main-dpi-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AB23) VOUT0_VSYNC */
			J722S_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
			J722S_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC26) VOUT0_PCLK */
			J722S_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (AC27) VOUT0_DE */
			J722S_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (W27) VOUT0_DATA0 */
			J722S_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA1 */
			J722S_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA2 */
			J722S_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA3 */
			J722S_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA4 */
			J722S_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA5 */
			J722S_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y26) VOUT0_DATA6 */
			J722S_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (Y27) VOUT0_DATA7 */
			J722S_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA8 */
			J722S_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AA27) VOUT0_DATA9 */
			J722S_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA10 */
			J722S_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA11 */
			J722S_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA12 */
			J722S_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA22) VOUT0_DATA13 */
			J722S_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AB26) VOUT0_DATA14 */
			J722S_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AB27) VOUT0_DATA15 */
			J722S_IOPAD(0x005c, PIN_OUTPUT, 1) /* (U27) GPMC0_AD8.VOUT0_DATA16 */
			J722S_IOPAD(0x0060, PIN_OUTPUT, 1) /* (U26) GPMC0_AD9.VOUT0_DATA17 */
			J722S_IOPAD(0x0064, PIN_OUTPUT, 1) /* (V27) GPMC0_AD10.VOUT0_DATA18 */
			J722S_IOPAD(0x0068, PIN_OUTPUT, 1) /* (V25) GPMC0_AD11.VOUT0_DATA19 */
			J722S_IOPAD(0x006c, PIN_OUTPUT, 1) /* (V26) GPMC0_AD12.VOUT0_DATA20 */
			J722S_IOPAD(0x0070, PIN_OUTPUT, 1) /* (V24) GPMC0_AD13.VOUT0_DATA21 */
			J722S_IOPAD(0x0074, PIN_OUTPUT, 1) /* (V22) GPMC0_AD14.VOUT0_DATA22 */
			J722S_IOPAD(0x0078, PIN_OUTPUT, 1) /* (V23) GPMC0_AD15.VOUT0_DATA23 */
			J722S_IOPAD(0x009c, PIN_OUTPUT, 1) /* (W26) GPMC0_WAIT1.VOUT0_EXTPCLKIN */
		>;
	};

        main_mcan0_pins_default: main-mcan0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x1dc, PIN_INPUT, 0) /* (C22) MCAN0_RX */
			J722S_IOPAD(0x1d8, PIN_OUTPUT, 0) /*(D22) MCAN0_TX */
		>;
	};
};

&main_gpio1 {
	status = "okay";
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	status = "okay";
	bootph-all;
};

&mcu_pmx0 {

	wkup_uart0_pins_default: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
			J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
			J722S_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
			J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
		>;
		bootph-all;
	};

	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0)	/* (C7) WKUP_I2C0_SCL */
			J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0)	/* (C6) WKUP_I2C1_SDA */
		>;
		bootph-all;
	};

	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */
			J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */
			J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) MCU_GPIO0_12 */
		>;
	};
};

&wkup_uart0 {
	/* WKUP UART0 is used by DM firmware */
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "reserved";
	bootph-all;
};

&wkup_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_i2c0_pins_default>;
	clock-frequency = <400000>;
	bootph-all;
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;
	bootph-all;

	exp1: gpio@23 {
		compatible = "ti,tca6424";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL",
				  "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#",
				  "CSI_VIO_SEL", "USB2.0_MUX_SEL",
				  "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2",
				  "LMK1_OE1", "LMK1_OE0",
				  "LMK2_OE0", "LMK2_OE1",
				  "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn",
				  "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN",
				  "USER_LED2", "MCAN0_STB",
				  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
				  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
				  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
		p01-hog {
			/* P01 - TRC_MUX_SEL */
			gpio-hog;
			gpios = <0 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "TRC_MUX_SEL";
		};
	};
};

&main_i2c2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <400000>;

	pca9543_0: i2c-mux@70 {
		compatible = "nxp,pca9543";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
	};

	pca9543_1: i2c-mux@71 {
		compatible = "nxp,pca9543";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x71>;
	};
};

&main_i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <100000>;

	exp2: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "DSI_Mux_SEL_2", "GPIO_eDP_ENABLE",
				  "DP0_PWR_SW_EN", "GPIO_OLDI_RSTn",
				  "GPIO_HDMI_RSTn", "HDMI_LS_OE",
				  "", "",
				  "DSI_GPIO0", "DSI_GPIO1",
				  "DSI_EDID", "IO_eDP_IRQ",
				  "OLDI_INT#", "HDMI_INTn",
				  "", "";

		interrupt-parent = <&main_gpio0>;
		interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		pinctrl-names = "default";
		pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>;
		bootph-all;

		p04-hog {
			/* P04 - GPIO_HDMI_RSTn */
			gpio-hog;
			gpios = <4 GPIO_ACTIVE_LOW>;
			output-low;
			line-name = "GPIO_HDMI_RSTn";
		};

		p03-hog {
			/* P03 - GPIO_OLDI_RSTn */
			gpio-hog;
			gpios = <3 GPIO_ACTIVE_LOW>;
			output-low;
			line-name = "GPIO_OLDI_RSTn";
		};

		p05-hog {
			/* P05 - HDMI_LS_OE */
			gpio-hog;
			gpios = <5 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "HDMI_LS_OE";
		};
	};

	sii9022: bridge-hdmi@3b {
		compatible = "sil,sii9022";
		reg = <0x3b>;
		interrupt-parent = <&exp2>;
		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
		#sound-dai-cells = <0>;
		sil,i2s-data-lanes = < 0 >;

		hdmi_tx_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/*
			 * HDMI can be serviced with 3 potential VPs -
			 * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1).
			 * For now, we will service it with DSS1 VP0.
			 */
			port@0 {
				reg = <0>;

				sii9022_in: endpoint {
					remote-endpoint = <&dss1_dpi0_out>;
				};
			};

			port@1 {
				reg = <1>;

				sii9022_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};
};

&sdhci0 {
	/*eMMC*/
	status = "okay";
	ti,driver-strength-ohm = <50>;
	disable-wp;
	bootph-all;
};

&sdhci1 {
	/* SD/MMC */
	status = "okay";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	bootph-all;
};

&ospi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;
	bootph-all;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		bootph-all;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			bootph-all;

			partition@0 {
				label = "ospi.tiboot3";
				reg = <0x00 0x80000>;
			};

			partition@80000 {
				label = "ospi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "ospi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "ospi.env";
				reg = <0x680000 0x40000>;
			};

			partition@6c0000 {
				label = "ospi.env.backup";
				reg = <0x6c0000 0x40000>;
			};

			partition@800000 {
				label = "ospi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "ospi.phypattern";
				reg = <0x3fc0000 0x40000>;
				bootph-all;
			};
		};
	};

	ospi0_nand: nand@0 {
		compatible = "spi-nand";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
		status = "disabled";

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi_nand.tiboot3";
				reg = <0x0 0x80000>;
			};

			partition@80000 {
				label = "ospi_nand.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "ospi_nand.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "ospi_nand.env";
				reg = <0x680000 0x40000>;
			};

			partition@6c0000 {
				label = "ospi_nand.env.backup";
				reg = <0x6c0000 0x40000>;
			};

			partition@2000000 {
				label = "ospi_nand.rootfs";
				reg = <0x2000000 0x5fc0000>;
			};

			partition@7fc0000 {
				label = "ospi_nand.phypattern";
				reg = <0x7fc0000 0x40000>;
			};
		};
	};
};

&cpsw3g {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins_default>;
};

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default>;

	cpsw3g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw_port2 {
	status = "disabled";
};

&mailbox0_cluster0 {
	status = "okay";
	mbox_r5_0: mbox-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster1 {
	status = "okay";
	mbox_mcu_r5_0: mbox-mcu-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster2 {
	status = "okay";
	mbox_c7x_0: mbox-c7x-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster3 {
	status = "okay";
	mbox_main_r5_0: mbox-main-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c7x_1: mbox-c7x-1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&wkup_r5fss0 {
	status = "okay";
};

&wkup_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
			<&wkup_r5fss0_core0_memory_region>;
};

&mcu_r5fss0 {
	status = "okay";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&main_r5fss0 {
	status = "okay";
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

&c7x_0 {
	status = "okay";
	mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
	memory-region = <&c7x_0_dma_memory_region>,
			<&c7x_0_memory_region>;
};

&c7x_1 {
	status = "okay";
	mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
	memory-region = <&c7x_1_dma_memory_region>,
			<&c7x_1_memory_region>;
};

&serdes_ln_ctrl {
	idle-states = <J722S_SERDES0_LANE0_USB>,
		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
};

&serdes0 {
	status = "okay";
	serdes0_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz0 1>;
	};
};

&serdes1 {
	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>;
	};
};

&usbss0 {
	status = "okay";
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	usb-role-switch;
};

&usbss1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb1_pins_default>;
	ti,vbus-divider;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "super-speed";
	phys = <&serdes0_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&pcie0_rc {
	status = "okay";
	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
};

&dss1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_dpi_pins_default>;

	assigned-clocks = <&k3_clks 241 0>,	/* DSS1-VP0 */
			  <&k3_clks 240 0>,	/* DSS1-VP1 */
			  <&k3_clks 245 0>;	/* DPI Output */

	assigned-clock-parents = <&k3_clks 241 2>,	/* PLL 17 HDMI */
				 <&k3_clks 240 1>,	/* PLL 18 DSI */
				 <&k3_clks 245 2>;	/* DSS1-DPI0 */
};

&dss1_ports {
	/* DSS1-VP0: DPI/HDMI Output */
	port@0 {
		reg = <0>;

		dss1_dpi0_out: endpoint {
			remote-endpoint = <&sii9022_in>;
		};
	};
};

&mcu_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan0_pins_default>;
	phys = <&transceiver0>;
};

&mcu_mcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan1_pins_default>;
	phys = <&transceiver1>;
};

&main_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan0_pins_default>;
	phys = <&transceiver2>;
};

&mcu_gpio0 {
	status = "okay";
};

  • 0 in reply to Vincent Wan
    TI__Guru 51503 points

    Hi Vincent, 

    Nothing looks to be out of place in the dts file. I am not sure what could be going on to cause mcu_mcan1 to go into bus-off state. However, I did confirm that the default SDK 10.0 image has MCAN working as expected for both mcu_mcan0 and mcu_mcan1 so you could try it out on the newest SDK release. If the issue still persists with SDK 10.0, then it could be some hardware issue, otherwise, most likely it is a software issue.

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Intellectual 450 points

    Hi Takuma,

    I found that in order for cansend to work without the bus-off message I need to enable both mcu_mcan0 and mcu_mcan1 at the same time using 'ip link':

    ip link set mcu_mcan0 up type can bitrate 500000
ip link set mcu_mcan1 up type can bitrate 500000
cansend mcu_mcan1 345#1122334455667788

    This is a strange requirement.

    Best regards,

    Vincent

  • 0 in reply to Vincent Wan
    TI__Guru 51503 points

    Hi Vincent,

    That is a strange behavior indeed. Let me check with the broader team on this. In the meantime, does the workaround to enable both mcu_mcan0 and 1 unblock your development?

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Intellectual 450 points

    Hi Takuma,

    Yes, this does seem to enable both mcu_mcan instances for socketcan, which is what we need.

    Best regards,

    Vincent