AM3358: What is absmax current for SPI1_SCLK (ball A13)?

Hello Geof,

Thank you for the query.

Are you able to draw the diagram on the configuration.

When you say 2 processors, there could be issues related to fail-safe and IO compatibility.

Regards,

Sreenivasa

Thanks for the reply!
Here is the basic topology. 2 different 3V3 processors connected to the same copper.

Hello Geof,

This is not a condition we would expect the IOs to be connected. Outputs being shorted through a low value series resistor.

Let me check with the device expert to get his thoughts.

Regards,

Sreenivasa

Hello Geof,

geof lipman said:

Our design has 2 processors sharing the same copper for the SPI bus. One drives the SPI bus while the other processor is booting.

I would like to know if the AM3358 pin circuit will be damaged if there is a spurious collision, whereby the line is driven low, but the AM3358 is trying to drive it high.

Are you able to share the use case for connecting the clock in the above configuration.

After power-up, do you have a way to ensure one of them drive the clock.

Regards,

Sreenivasa

We have a user requirement that our product provides user feedback immediately after power-up.

User feedback is provided via an OLED screen which is controlled by the SPI bus.

The boot time for our main processor, the AM3358, is too long, so we use a small STM MCU to provide user feedback during the boot time of the AM3358.

Our firmware design is such that

1. during boot, the AM3358 SPI pins are set to be high impedance.

2. the STM MCU SPI pins are initially driven, and then set to high impedance before the AM3358 takes over.

The design works as described above.

What I am trying to understand is what might happen if there is a problem, whereby both processors are trying to access the SPI bus at the same time. Will the AM3358 be damaged?

Using 27 ohm resistors, the maximum current is limited to 3.3V/54 = 61mA

Will this current damage the AM3358?

Is there a time period after which the AM3358 will be damaged?

Thanks!

Hello Geof,

Thank you.

geof lipman said:

What I am trying to understand is what might happen if there is a problem, whereby both processors are trying to access the SPI bus at the same time.

I assume this happens every power-up.

What is the frequency of occurrence and the current flow duration.

Regards,

Sreenivasa

If the firmware is working properly, there will be no contention, and zero current flow.

I am trying to find out what happens if there is a malfunction.

So I cannot specify what the duration is because that is the question I am asking.

What is the absolute maximum current and duty cycle of the AM3358 SPI1_SCLK pin?

Hello Geof,

Thank you.

This is not an expected use case for the AM335x device.  We never validated any DC current over 6mA, so I’m not able to say what will happen during this condition.  There is a chance the device appears to works as expected after this condition, but the IO and the on-die connectivity may be damaged such that it creates what we call a walking wounded device that may experience an issue with long term reliability.

 If the concern is with product reliability, the recommendation is to use a bus FET switch configured such that it ensures only one clock source is connected to the signal.

Regards,

Sreenivasa