[FAQ] Using DDR IBIS Models for AM64x, AM62x, AM62Ax, AM62Px

The DDR Controller and PHY in Sitara processors is a flexible interface which can be used with LPDDR4 or DDR4. There are many settings available to fine-tune the signal timing on this interface. These settings include ODT options, pullups, pulldowns, temp etc. IBIS modeling can be used to fine tune the set of options for a given PCB. That said, understanding the mapping between the various IBIS models and the corresponding register configuration options is critical to doing this correctly. This article is intended to help bridge that gap so that users can properly model their memory interface in simulation.
NOTE: TI does not support timing analysis with IBIS simulations. Rather, customers are encouraged to use the IBIS models for Signal Integrity (SI) analysis. As far as the timing goes, please follow the routing guidelines and length/skew matching requirements in the DDR Board Design and Layout Guidelines found on the product page on ti.com. 

IBIS Structure

In the IBIS file for the device (see product page for the device for the IBIS file), each pin on the device is listed with a corresponding model selector. For example:

[Pin] Signal_name model_name

K5 DDR0_A0 DDR_SE
R1 DDR0_CK0 DDR_DIFF_P
P1 DDR0_CK0_N DDR_DIFF_N

Address and data bits are examples of a Single Ended IO (DDR_SE). Clock and DQS are examples of Differential IO (DDR_DIFF_P and DDR_DIFF_N)

Further down in the file, each model selector will have a number of available models for the given IO cell. For example:

[Model Selector] DDR_SE
lpddr4_ocd_40p_40n_lt driver with 40 ohms pullup and 40 ohms pulldown strength, max slew rate
lpddr4_ocd_48p_48n_lt driver with 48 ohms pullup and 48 ohms pulldown strength, max slew rate
lpddr4_ocd_60p_60n_lt driver with 60 ohms pullup and 60 ohms pulldown strength, max slew rate
etc.

[Model Selector] DDR_DIFF_P
lpddr4_ocd_40p_40n_p_lt driver with 40 ohms pullup and 40 ohms pulldown strength, max slew rate
lpddr4_ocd_48p_48n_p_lt driver with 48 ohms pullup and 48 ohms pulldown strength, max slew rate
lpddr4_ocd_60p_60n_p_lt driver with 60 ohms pullup and 60 ohms pulldown strength, max slew rate
etc.

Each of the models above corresponds to the IO cell behavior given a specific set of configuration options

Register Mapping

Each model has the following structure:

For writes:
<MemoryType>_ocd_<pullup driver>_<pulldown driver>_<temp>

For reads:
<MemoryType>_odt_<termination>_<temp>

LPDDR4 Example

The AM62Px EVM with LPDDR4 has these parameter settings in the DDR Register Configuration in Sysconfig:

DDR Controller:

• Driver Pull-Up/Down Lane 0/1 DQ/DM/DQS (DQ/DQS/DM driver): 40ohm
• Driver Pull-Down CA[5:0] (CA driver): 40ohm
• Driver Pull-Down CSn (CSn driver): 80ohm
• Driver Pull-Down CK (CKp/n driver): 40ohm
• ODT Pull-Down Lane 0/1 DQ/DM/DQS (DQ/DQS/DM termination): 48ohm

DDR Memory:

• Drive Strength: Pull-Down (DQ/DQS/DM driver): 48ohm
• Termination: DQ ODT (DQ/DQS/DM termination): 48ohm
• Termination: CA ODT (CA/CSn/CKp/n termination): 80ohm

A simulation for high temp conditions would use these models:

• lpddr4_ocd_40p_40n_ht for Controller DQ/DM driver for writes
• lpddr4_ocd_40p_40n_p_ht for Controller DQSp driver for writes
• lpddr4_ocd_40p_40n_n_ht for Controller DQSn driver for writes
• lpddr4_ocd_40p_40n_ht for Controller CA[5:0] driver
• lpddr4_ocd_80p_80n_ht for Controller CSn driver
• lpddr4_ocd_40p_40n_p_ht for Controller CKp driver
• lpddr4_ocd_40p_40n_n_ht for Controller CKn driver
• lpddr4_odt_48_ht for Controller DQ/DM ODT for reads
• lpddr4_odt_48_diff_ht for Controller DQSp/n ODT for reads