Dear E2E:
I have a question about McASP on DSP OMAP-L138:
1. Will AFSX and ACLKX be running if McASP in “receive” mode?
2. Are AHCLKX/R clocks exactly synchronous (no delay) to ACLKX/R when AHCLKX/R divider is /1?
3. If there is a delay between AHCLKX/R and ACLKX/R – where is a timing? I could not find in SMOMAPL138 DS (SLVSAQ9) the timing delay between AHCLKX/R and ACLKX/R.
4. Can you please provide this timing for the AHCLKX/R to ACLKX/R?
5. The timing which is DS SMOMAPL138 (SLVSAQ9) – page153-157 has the parameters 5 - 8. Are these parameters 5 - 8 reference to AFSR/X, ACLKR/X, AXR0n – pins? Usually the timing is referenced to external pins.
6. At the same time – the parameters 5 - 8 numbers are depended of the direction on AHCLKR/X (internal/external). And the direction of ACLKR/X does not matter? Are these tables on DS page 153 and 155 correct?
Thank you for your help,
Boris Ruvinsky