Can't access ulpi-phy side registers

GAN,

Have you provided the correct details in your board file? for port number. connection mode etc?

AJAY

Thanks Ajay for your attention.

The following part is copied from my board_xxx.c. If it's not detail enough, I can paste the total file.

-----------------------------------------------

static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {

    .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
    .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
    .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,

    .phy_reset  = true,
    .reset_gpio_port[0]  = _ISP1504_RST_IO, // It's a GPIO
    .reset_gpio_port[1]  = -EINVAL,
    .reset_gpio_port[2]  = -EINVAL
};

...

usb_ehci_init(&ehci_pdata);

-----------------------------------------------

I also dumped some registers of the USB host, they are dumped just when the ehci-omap.ko is installed (after the failed software reset):

-----------------------------------------------

[    7.876556]   TLL_SYSSTATUS: 00000001                                                                                                      
[    7.880950]   TLL_IRQSTATUS: 00000000                                                                                                      
[    7.885284]   TLL_IRQENABLE: 00000000                                                                                                      
[    7.889678]   TLL_SHARECONF: 00000060                                                                                                      
[    7.894073]   TLL_CHANCONF0: 000006d8                                                                                                      
[    7.898406]   TLL_CHANCONF1: 000006d8                                                                                                      
[    7.902832]   TLL_CHANCONF2: 000006d8                                                                                                                                                                                                           
[    7.914794]   UHH_REVISION  : 00000010                                                                                                     
[    7.919281]   UHH_SYSCONFIG : 0000110c                                                                                                     
[    7.923706]   UHH_SYSSTATUS : 00000007                                                                                                     
[    7.928192]   UHH_HOSTCONFIG: 00000100                                                                                                     
[    7.932678]   UHH_DEBUG_CSR : 00000020                                                                                                     
[    7.937103]   EHCI_HCSPARAMS  : 00001313                                                                                                   
[    7.941772]   EHCI_HCCPARAMS  : 00000016

-----------------------------------------------

GAN,

The board file data and register dump looks fine to me. You told that PHY works fine if hardware reset, clock are given?..Do you see any issue

with PHY if no hardware reset is done? Do you see correct 60MHz clock to PHY?

Ajay

The 60Mhz clock (from host to isp1504) is fine, after the hardware reset is done, the PHY works okay. Without the hardware reset, the PHY doesn't work.

But the PHY isp1504 looks like always working as it's default mannor, any time when I tried to modify the value of it's registers, I always get the time-out issue.

The soft reset function in the source 'ehci-omap.c' also failed for the time out issue (The highest bit of INSNREG05_UPLI is always 1, it seems the transmission between the port and PHY never ends).

What I need to do is that successfully reading from or writing to the registers of ISP1504. Any good ideas?

GAN

Hi,

we had the same problem with the ULPI PHY  SMSC3320(Attention: SMSC3320 has also other bugs, see TI forums)  on the  AM3517.

INSNREG05_ULPI  works correct !!! after the CF Flag (configure flag) of the EHCI register CONFIGFLAG (see also OMAP35xx manual, AM3517 register address 0x48064850)

is set to one. 

There is no need to touch any other EHCI register after HW reset. Needed is clock, pad and all other initialization of the UHH module, see also other initialization sample code.

I think the LINUX driver code does not correct handle this bit in the initialization routine of the  PHY  (software reset, the function return value of the PHY control bit is not checked),

the Phy works also without software reset (needed is an hardware reset on the phy pin)!

With best regards

Steffen

Hi everybody,

I obtain the same behaviour (not needed of soft reset, but phy reset timeout at every boot), using dm3730 connected to Texas TUSB1210 phy.

Any help is very appreciated.

Raffaele