In hardware design guide, (Table 2-5) SRIO RefClk to be between 156.25MHz ~ 312.5MHz.
But in SRIO user guide (SPRUGW1), page 2-13 and Page 2-4 told us that 125MHz can be used as RefClk
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
That is an error SRIO User's Guide. User's Guides should not contain information that is specific to a component since they are more generic and usually support a number of components. The reference to 125MHz will be removed from the next revision of that document. Also note that there are only three frequencies supported for the SRIO reference clock. These frequencies are 156.25MHz, 250MHz and 312.5MHz. Your statement above implies that all frequencies between 156.25MH and 312.5MHz are valid. This is not true.
There is a nice table in this post that shows the CFGRX/TX and CFGPLL settings for that various supported refclks and data rates.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/114940/413828.aspx#413828
Regards,
Travis