PROCESSOR-SDK-J784S4: CddIpc gCslR5MpuCfg Configuration for 1 GB DDR

Calin Harangus

Tool/software:

Hello TI forum,

I was successfully tested on EVM the CddIPC provided by this example: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1356059/faq-tda4ah-q1-cdd-ipc-app-example-running-on-mcu1_0-communicating-with-another-r5-core. Now, the problem that we have is that on our board we have only a 1GB DDR instead of 4GB as EVM, mapped starting with address 0x80000000. How can I configure the Regions from CddIpcR5Mpu.c ? Where can I find the documentation to explain the Regions defined in gCslR5MpuCfg?

Thank you !

Best regards,

Calin Harangus

over 1 year ago

0 Kevin S over 1 year ago

TI__Mastermind 38560 points

Thanks for pointing to the example, we will loop in the author of the mentioned thread.

Regards,
Kevin

0 Tarun Mukesh Puvvada over 1 year ago in reply to Kevin S

TI__Guru 50176 points

Hello,

Calin Harangus said:
Now, the problem that we have is that on our board we have only a 1GB DDR instead of 4GB as EVM, mapped starting with address 0x80000000

Even if you change the DDR size the starting address will not be changed from 0x80000000.

For IPC , what cores you want to communicate with and not ,based on that you can change the reserved memory regions. This will be custom specific and mpu configuration need to done according to freeRTOS standards if you are using freeRTOS OS.

Regards

Tarun Mukesh

0 Calin Harangus over 1 year ago in reply to Tarun Mukesh Puvvada

Prodigy 200 points

Hello Tarun,

I want the IPC for cores mcu1_0 and mcu2_0. Yes, we are using freeRTOS. Anyway, de default configuration that you provided in the example mentioned above, has the IPC Shared Memory at address 0xAC000000 with size CSL_ARM_R5_MPU_REGION_SIZE_32MB. This should fit in our 1 GB. Still the application doesn't start with this configuration. It goes directly to HwiP_prefetch_abort_handler(). Maybe we didn't configured properly our lds file.

Do you have a hint for us where should we look? Or maybe an example of 1 GB lds file configuration?

Thank you very much!

Best regards,

Calin

0 Tarun Mukesh Puvvada over 1 year ago in reply to Calin Harangus

TI__Guru 50176 points

Hello Calin,

Can you provide me the call stack from where it is going to HwiP_prefetch_abort_handler().

We don't have any 1 GB lds file configuration.

Regards

Tarun Mukesh

0 Calin Harangus over 1 year ago in reply to Tarun Mukesh Puvvada

Prodigy 200 points

Hi Tarun,

Here is a snapshot from the callstack:

Thank you!

Best regards,

Calin Harangus

0 Tarun Mukesh Puvvada over 1 year ago in reply to Calin Harangus

TI__Guru 50176 points

Hello Calin,

Thanks for sharing the information.

It appears to be an issue in the MPU configuration itself and resulting in abort.Is it possible to share your MPU configuration.

Regards

Tarun Mukesh

0 Calin Harangus over 1 year ago in reply to Tarun Mukesh Puvvada

Prodigy 200 points

Hi Tarun,

Here is my CddIpcMpu.c:

Fullscreen CddIpcR5Mpu.c Download

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/**
 *  \file     CddIpcR5Mpu.c
 *
 *  \brief    This file defines R5 MPU configurations
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdlib.h>
#include <stdint.h>
#include <hw_include/arch/lld_arch.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
/** \brief The CSL startup code, uses gCslR5MpuCfg to define MPU configurations
 *          In cases where default configurations requires and override,
 *          applications could define this variable with required configuration
 *
 *          In this application, we would require to mark the shared area as
 *          non-cacheable and shared. Defined in regionId 7
 */
#if defined (BUILD_MCU1_0)
const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]
__attribute__((section(".CDD_IPC_MPU_CFG_OCMRAM"))) =
#else
/* const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] __attribute__ ((section(".CDD_IPC_MPU_CFG_OCMRAM"))) =  No support for other
    cores/compilers at this point */
const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
#endif
{
    {
        /* Region 0 configuration: complete 32 bit address space = 4Gbits */
        .regionId         = 0U,
        .enable           = 1U,
        .baseAddr         = 0x0U,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 1U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)FALSE,
        .cachePolicy      = 0U,
        .memAttr          = 0U,
    },
    {
        /* Region 1 configuration: 128 bytes memory for exception vector execution */
        .regionId         = 1U,
        .enable           = 1U,
        .baseAddr         = 0x0U,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128B,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 2 configuration: 512 KB OCMS RAM */
        .regionId         = 2U,
        .enable           = 1U,
        .baseAddr         = 0x41C00000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 3 configuration: 2 MB MCMS3 RAM */
        .regionId         = 3U,
        .enable           = 1U,
        .baseAddr         = 0x70000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 4 configuration: 2 GB DDR RAM */
        .regionId         = 4U,
        .enable           = 1U,
        .baseAddr         = 0x80000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1GB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 5 configuration: 64 KB BTCM */
        .regionId         = 5U,
        .enable           = 1U,
        .baseAddr         = 0x41010000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_64KB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },
    {
        /* Region 6 configuration: 128 MB FSS DAT */
        .regionId         = 6U,
        .enable           = 1U,
        .baseAddr         = 0x50000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128MB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },
    {
        /* Region 7 configuration: 32 MB for IPC Shared memory */
        .regionId         = 7U,
        .enable           = 1U,
        .baseAddr         = 0xAC000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32MB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 1U,
        .cacheable        = (uint32_t)FALSE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },
};

/*EoF*/

And following is the linker file with MCU1_0 and MCU2_0 configuration:

Fullscreen linker_r5f_common_freertos.txt Download

/*=========================*/
/*     Linker Settings     */
/*=========================*/

--retain="*(.bootCode)"
--retain="*(.startupCode)"
--retain="*(.startupData)"
--retain="*(.irqStack)"
--retain="*(.fiqStack)"
--retain="*(.abortStack)"
--retain="*(.undStack)"
--retain="*(.svcStack)"

--fill_value=0
--stack_size=0x4000
--heap_size=0x8000
--entry_point=_freertosresetvectors

-stack  0x4000  /* SOFTWARE STACK SIZE */
-heap   0x8000  /* HEAP AREA SIZE      */

--define FILL_PATTERN=0xFEAA55EF
--define FILL_LENGTH=0x100

__IRQ_STACK_SIZE   = 0x1000;  /* IRQ stack size */
__FIQ_STACK_SIZE   = 0x0100;  /* FIQ stack size */
__ABORT_STACK_SIZE = 0x0100;  /* Abort stack size */
__UND_STACK_SIZE   = 0x0100;  /* Undefined instruction mode stack size */
__SVC_STACK_SIZE   = 0x0100;  /* Supervisor mode stack size */

/* DDR memory map */
#define CONCAT(a, b)                a##b

#define DDR0_ALLOCATED_START        (0x80000000)

#define MCU1_0_DDR_SIZE             (0x10000000) /* 256MB */
#define MCU2_0_DDR_SIZE             (0x10000000) /* 256MB */
#define DSP0_DDR_SIZE               (0x01000000) /* 16MB */
#define DSP1_DDR_SIZE               (0x01000000) /* 16MB */
#define WAKEUP_SIZE                 (0x10000000) /* 256MB */

#define MCU1_0_DDR_SPACE_START      (DDR0_ALLOCATED_START)
#define MCU1_0_DDR_SPACE_END        (MCU1_0_DDR_SPACE_START + MCU1_0_DDR_SIZE)
#define MCU2_0_DDR_SPACE_START      (MCU1_0_DDR_SPACE_END)
#define MCU2_0_DDR_SPACE_END        (MCU2_0_DDR_SPACE_START + MCU2_0_DDR_SIZE)
#define DSP0_DDR_SPACE_START        (MCU2_0_DDR_SPACE_END)
#define DSP0_DDR_SPACE_END          (DSP0_DDR_SPACE_START + DSP0_DDR_SIZE)
#define DSP1_DDR_SPACE_START        (DSP0_DDR_SPACE_END)
#define DSP1_DDR_SPACE_END          (DSP1_DDR_SPACE_START + DSP1_DDR_SIZE)
#define WAKEUP_DDR_SPACE_START      (DSP1_DDR_SPACE_END)
#define WAKEUP_DDR_SPACE_END        (WAKEUP_DDR_SPACE_START + WAKEUP_SIZE)

#define MCU_DDR_SIZE(mcu)           CONCAT(mcu, _DDR_SIZE)
#define MCU_DDR_SPACE_START(mcu)    CONCAT(mcu, _DDR_SPACE_START)
#define MCU_DDR_SPACE_END(mcu)      CONCAT(mcu, _DDR_SPACE_END)


MEMORY
{
    /* MCU R5F TCM Local View */
    MCU_R5F_TCMA_VECS       (X) : ORIGIN = 0x00000000 LENGTH = 0x00000040
    MCU_R5F_TCMA            (X) : ORIGIN = 0x00000040 LENGTH = 0x00007FC0
    MCU_R5F_TCMB_VECS       (X) : ORIGIN = 0x41010000 LENGTH = 0x00000040
    MCU_R5F_TCMB            (X) : ORIGIN = 0x41010040 LENGTH = 0x00007FC0

    /*- Refer user guide for details on persistence of these sections -*/
    OCMC_RAM_BOARD_CFG   (RWIX) : ORIGIN = 0x41C80000 LENGTH = 0x00002000
    OCMC_RAM_SCISERVER   (RWIX) : ORIGIN = 0x41C82000 LENGTH = 0x00060000
    OCMC_RAM             (RWIX) : ORIGIN = 0x41CE3100 LENGTH = 0x0001AA00
    OCMC_RAM_X509_HEADER (RWIX) : ORIGIN = 0x41CFDB00 LENGTH = 0x00000500

    /*========================J784S4 MCMS3 LOCATIONS ===================*/
    /*---------- J784S4 Reserved Memory for ARM Trusted Firmware -------*/
    MSMC3_ARM_FW  (RWIX)        : ORIGIN = 0x70000000 LENGTH = 0x00020000   /* 128KB */
    MSMC3         (RWIX)        : ORIGIN = 0x70020000 LENGTH = 0x007D0000   /* 8MB - 192KB */
    /*------------- J784S4 Reserved Memory for DMSC Firmware -----------*/
    MSMC3_DMSC_FW (RWIX)        : ORIGIN = 0x707F0000 LENGTH = 0x00010000   /* 64KB */

    /*======================= J784S4 DDR LOCATION =======================*/
    MCU1_0_DDR (RWIX)          : ORIGIN = MCU_DDR_SPACE_START(MCU1_0) LENGTH = MCU_DDR_SIZE(MCU1_0)
    MCU2_0_DDR (RWIX)          : ORIGIN = MCU_DDR_SPACE_START(MCU2_0) LENGTH = MCU_DDR_SIZE(MCU2_0)
    DSP0_DDR (RWIX)            : ORIGIN = MCU_DDR_SPACE_START(DSP0) LENGTH = MCU_DDR_SIZE(DSP0)
    DSP1_DDR (RWIX)            : ORIGIN = MCU_DDR_SPACE_START(DSP1) LENGTH = MCU_DDR_SIZE(DSP1)
    WAKEUP_DDR (RWIX)          : ORIGIN = MCU_DDR_SPACE_START(WAKEUP) LENGTH = WAKEUP_SIZE
}

#define MCU_DDR(mcu)           CONCAT(mcu, _DDR)

/* Section Definitions */
SECTIONS
{
    .freertosrstvectors     : {} palign(8)                      > MCU_R5F_TCMA_VECS
    .bootCode               : {} palign(8)                      > MCU_R5F_TCMA
    .startupCode            : {} palign(8)                      > MCU_R5F_TCMA
    .startupData            : {} palign(8)                      > MCU_R5F_TCMA, type = NOINIT
    .text                   : {} palign(8)                      > MCU_DDR(CURRENT_MCU)
    GROUP {
        .text.hwi           : palign(8)
        .text.cache         : palign(8)
        .text.mpu           : palign(8)
        .text.boot          : palign(8)
    }                                                           > MCU_DDR(CURRENT_MCU)
    .const                  : {} palign(8)                      > MCU_DDR(CURRENT_MCU)
    .rodata                 : {} palign(8)                      > MCU_DDR(CURRENT_MCU)
    .cinit                  : {} palign(8)                      > MCU_DDR(CURRENT_MCU)
    .bss                    : {} align(4)                       > MCU_DDR(CURRENT_MCU)
    .far                    : {} align(4)                       > MCU_DDR(CURRENT_MCU)
    .data                   : {} palign(128)                    > MCU_DDR(CURRENT_MCU)
    .sysmem                 : {}                                > MCU_DDR(CURRENT_MCU)
    .data_buffer            : {} palign(128)                    > MCU_DDR(CURRENT_MCU)
    .bss.devgroup           : {*(.bss.devgroup*)} align(4)      > MCU_DDR(CURRENT_MCU)
    .const.devgroup         : {*(.const.devgroup*)} align(4)    > MCU_DDR(CURRENT_MCU)
    .boardcfg_data          : {} align(4)                       > MCU_DDR(CURRENT_MCU)

    /* USB or any other LLD buffer for benchmarking */
    .benchmark_buffer (NOLOAD) {} ALIGN (8)                     > MCU_DDR(CURRENT_MCU)

    .stack      : {} align(4)                                   > MCU_DDR(CURRENT_MCU)  (HIGH)

    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)          > MCU_DDR(CURRENT_MCU)  (HIGH)
    RUN_START(__IRQ_STACK_START)
    RUN_END(__IRQ_STACK_END)

    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)          > MCU_DDR(CURRENT_MCU)  (HIGH)
    RUN_START(__FIQ_STACK_START)
    RUN_END(__FIQ_STACK_END)

    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)        > MCU_DDR(CURRENT_MCU)  (HIGH)
    RUN_START(__ABORT_STACK_START)
    RUN_END(__ABORT_STACK_END)

    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)          > MCU_DDR(CURRENT_MCU)  (HIGH)
    RUN_START(__UND_STACK_START)
    RUN_END(__UND_STACK_END)

    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)          > MCU_DDR(CURRENT_MCU)  (HIGH)
    RUN_START(__SVC_STACK_START)
    RUN_END(__SVC_STACK_END)


    /* Additional sections settings     */
        McalTextSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR
        {
            .=align(4);
            __linker_spi_text_start = .;
            . += FILL_LENGTH;
            *(SPI_TEXT_SECTION)
            *(SPI_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_text_end = .;

            .=align(4);
            __linker_gpt_text_start = .;
            . += FILL_LENGTH;
            *(GPT_TEXT_SECTION)
            *(GPT_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_text_end = .;

            .=align(4);
            __linker_dio_text_start = .;
            . += FILL_LENGTH;
            *(DIO_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_text_end = .;

            .=align(4);
            __linker_eth_text_start = .;
            . += FILL_LENGTH;
            *(ETH_TEXT_SECTION)
            *(ETH_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_text_end = .;

            .=align(4);
            __linker_ethtrcv_text_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_text_end = .;

            .=align(4);
            __linker_can_text_start = .;
            . += FILL_LENGTH;
            *(CAN_TEXT_SECTION)
            *(CAN_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_text_end = .;

            .=align(4);
            __linker_wdg_text_start = .;
            . += FILL_LENGTH;
            *(WDG_TEXT_SECTION)
            *(WDG_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_text_end = .;

            .=align(4);
            __linker_pwm_text_start = .;
            . += FILL_LENGTH;
            *(PWM_TEXT_SECTION)
            *(PWM_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_text_end = .;

            __linker_adc_text_start = .;
            . += FILL_LENGTH;
            *(ADC_TEXT_SECTION)
            *(ADC_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_text_end = .;

            .=align(4);
            __linker_cdd_ipc_text_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_TEXT_SECTION)
            *(CDD_IPC_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_text_end = .;

        }
        McalConstSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR
        {
            .=align(4);
            __linker_spi_const_start = .;
            . += FILL_LENGTH;
            *(SPI_CONST_32_SECTION)
            *(SPI_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_const_end = .;

            .=align(4);
            __linker_gpt_const_start = .;
            . += FILL_LENGTH;
            *(GPT_CONST_32_SECTION)
            *(GPT_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_const_end = .;

            .=align(4);
            __linker_dio_const_start = .;
            . += FILL_LENGTH;
            *(DIO_CONST_32_SECTION)
            *(DIO_CONST_UNSPECIFIED_SECTION)
            *(DIO_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_const_end = .;

            .=align(4);
            __linker_can_const_start = .;
            . += FILL_LENGTH;
            *(CAN_CONST_8_SECTION)
            *(CAN_CONST_32_SECTION)
            *(CAN_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_const_end = .;

            .=align(4);
            __linker_eth_const_start = .;
            . += FILL_LENGTH;
            *(ETH_CONST_32_SECTION)
            *(ETH_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_const_end = .;

            .=align(4);
            __linker_ethtrcv_const_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_CONST_32_SECTION)
            *(ETHTRCV_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_const_end = .;

            .=align(4);
            __linker_wdg_const_start = .;
            . += FILL_LENGTH;
            *(WDG_CONST_32_SECTION)
            *(WDG_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_const_end = .;

            .=align(4);
            __linker_pwm_const_start = .;
            . += FILL_LENGTH;
            *(PWM_CONST_32_SECTION)
            *(PWM_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_const_end = .;

            .=align(4);
            __linker_adc_const_start = .;
            . += FILL_LENGTH;
            *(ADC_CONST_32_SECTION)
            *(ADC_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_const_end = .;

            .=align(4);
            __linker_cdd_ipc_const_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_CONST_32_SECTION)
            *(CDD_IPC_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_const_end = .;
        }

        McalInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR
        {
            .=align(4);
            __linker_spi_init_start = .;
            . += FILL_LENGTH;
            *(SPI_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_init_end = .;

            .=align(4);
            __linker_gpt_init_start = .;
            . += FILL_LENGTH;
            *(GPT_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_init_end = .;

            .=align(4);
            __linker_pwm_init_start = .;
            . += FILL_LENGTH;
            *(PWM_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_init_end = .;

            .=align(4);
            __linker_dio_init_start = .;
            . += FILL_LENGTH;
            *(DIO_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_init_end = .;

            .=align(4);
            __linker_eth_init_start = .;
            . += FILL_LENGTH;
            *(ETH_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_init_end = .;

            .=align(4);
            __linker_ethtrcv_init_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION)
            *(ETHTRCV_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_init_end = .;

            .=align(4);
            __linker_can_init_start = .;
            . += FILL_LENGTH;
            *(CAN_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_init_end = .;

            .=align(4);
            __linker_wdg_init_start = .;
            . += FILL_LENGTH;
            *(WDG_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_init_end = .;

            .=align(4);
            __linker_adc_init_start = .;
            . += FILL_LENGTH;
            *(ADC_DATA_INIT_UNSPECIFIED_SECTION)
            *(ADC_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_init_end = .;

            .=align(4);
            __linker_cdd_ipc_init_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION)
            *(CDD_IPC_DATA_INIT_32_SECTION)
            *(CDD_IPC_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_init_end = .;
        }
        McalNoInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR, type = NOINIT
        {
            .=align(4);
            __linker_spi_no_init_start = .;
            . += FILL_LENGTH;
            *(SPI_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_no_init_end = .;

            .=align(4);
            __linker_gpt_no_init_start = .;
            . += FILL_LENGTH;
            *(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_no_init_end = .;

            .=align(4);
            __linker_dio_no_init_start = .;
            . += FILL_LENGTH;
            *(DIO_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_no_init_end = .;

            .=align(4);
            __linker_eth_no_init_start = .;
            . += FILL_LENGTH;
            *(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_no_init_end = .;

            .=align(4);
            __linker_ethtrcv_no_init_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(ETHTRCV_DATA_NO_INIT_16_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_no_init_end = .;

            .=align(4);
            __linker_can_no_init_start = .;
            . += FILL_LENGTH;
            *(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(CAN_DATA_NO_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_no_init_end = .;

            .=align(4);
            __linker_wdg_no_init_start = .;
            . += FILL_LENGTH;
            *(WDG_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_no_init_end = .;

            .=align(4);
            __linker_pwm_no_init_start = .;
            . += FILL_LENGTH;
            *(PWM_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_no_init_end = .;

            __linker_adc_no_init_start = .;
            . += FILL_LENGTH;
            *(ADC_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_no_init_end = .;

            __linker_cdd_ipc_no_init_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(CDD_IPC_DATA_NO_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_no_init_end = .;

        }
        /* Example Utility specifics */
        VariablesAlignedNoInitSection : align=8, load > MCU1_0_DDR, type = NOINIT
        {
            .=align(8);
            __linker_cdd_ipc_no_init_align_8b_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
            .=align(8);
            . += FILL_LENGTH;
            __linker_cdd_ipc_no_init_align_8b_end = .;
        }
        /* Example Utility specifics */
        UtilityNoInitSection : align=4, load > MCU1_0_DDR, type = NOINIT
        {
            .=align(4);
            __linker_utility_no_init_start = .;
            . += FILL_LENGTH;
            *(EG_TEST_RESULT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_utility_no_init_end = .;
        }
        SciClientBoardCfgSection : align=128, load > MCU1_0_DDR, type = NOINIT
        {
            .=align(128);
            __linker_boardcfg_data_start = .;
            . += FILL_LENGTH;
            *(.boardcfg_data)
            .=align(128);
            . += FILL_LENGTH;
            __linker_boardcfg_data_end = .;
        }
        /* This section is used for descs and ring mems. It's best to have
         * it in OCMRAM or MSMC3 */
        McalUdmaSection : fill=FILL_PATTERN, align=128, load > MSMC3
        {
            .=align(128);
            __linker_eth_udma_desc_start = .;
            . += FILL_LENGTH;
            *(ETH_UDMA_DESC_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_udma_desc_end = .;

            .=align(128);
            __linker_eth_udma_ring_start = .;
            . += FILL_LENGTH;
            *(ETH_UDMA_RING_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_udma_ring_end = .;
        }
        McalTxDataSection : fill=FILL_PATTERN, align=128, load > MCU1_0_DDR, type = NOINIT
        {
            .=align(128);
            __linker_eth_tx_data_start = .;
            . += FILL_LENGTH;
            *(ETH_TX_DATA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_tx_data_end = .;
        }
        McalRxDataSection : fill=FILL_PATTERN, align=128, load > MCU1_0_DDR, type = NOINIT
        {
            .=align(128);
            __linker_eth_rx_data_start = .;
            . += FILL_LENGTH;
            *(ETH_RX_DATA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_rx_data_end = .;
        }
}

Thank you very much!

Best regards,

Calin Harangus

Processors

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PROCESSOR-SDK-J784S4: CddIpc gCslR5MpuCfg Configuration for 1 GB DDR