AM62A7: RAM size configuration in the u-boot dts file

Jay Kaneria said:

Here i can see that two line in "reg" value. each line contains 2GB size which makes 4GB of RAM. Am I correct?

Hi Jay, yes this is correct.

https://dev.ti.com/tirex/explore/node?node=A__AUdU9gDSH2zZk3WsPA6pcA__AM62A-ACADEMY__WeZ9SsL__LATEST

You will need other changes as well, if you are using a different DDR part. The bank number is defined in the CONFIG_NR_DRAM_BANKS=2 in am62ax_evm_a53_defconfig file.

Please refer: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1005549/tda4vm-uboot-start-failed-when-ddr-4g-changed-to-2g/3720455#3720455

https://www.ti.com/tool/download/DDR-CONFIG-AM62A/1.0.0

Regards,
Aparna

Hi Aparna, 

Thank you for providing the references for ddr changes.

I have made below changes in EVK u-boot source for changed ddr from 4GB to 1GB(single rank).

diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index 5f1bd32a755..331dd58a4b4 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -26,9 +26,8 @@

        memory@80000000 {
                device_type = "memory";
-               /* 4G RAM */
-               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000000 0x80000000>;
+               /* 1G RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
                bootph-pre-ram;
        };

diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index f727b5f8258..a045f5f21f8 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -30,9 +30,8 @@

        memory@80000000 {
                device_type = "memory";
-               /* 4G RAM */
-               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000000 0x80000000>;
+               /* 1G RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
        };

        reserved-memory {
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 2ec7f4b5e97..7147294d95d 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SOC_K3_AM62A7=y
 CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
 CONFIG_TARGET_AM62A7_A53_EVM=y
diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h
index 7eef6644dd7..abbcc2745fc 100644
--- a/include/configs/am62ax_evm.h
+++ b/include/configs/am62ax_evm.h
@@ -11,10 +11,6 @@
 #include <config_distro_bootcmd.h>
 #include <environment/ti/mmc.h>

-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1            0x880000000
-
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>

Also, What are the changes in struct mm_region am64_mem_map[NR_MMU_REGIONS] in the file arch/arm/mach-k3/arm64-mmu.c would be required? I didn't understand this change from j721e reference.

Apart, from the above changes, I have generated the k3-am62Ax-ddr-config.dtsi from sysconfig tool and coping into k3-am62a-ddr-1866mhz-32bit.dtsi file. Am I coping into correct file?

We are using the spl for boot. Do we need any other file that generated by the ddr configuration tool? 

Regards,

Jay

Jay Kaneria said:

Also, What are the changes in struct mm_region am64_mem_map[NR_MMU_REGIONS] in the file arch/arm/mach-k3/arm64-mmu.c would be required?

Hi Jay,

Looks like the j721e_mem_map has been modified to contain one region as the user wants to use a single bank DDR instead of a dual bank one. 

Please reciprocate the change as mentioned on the thread. Meanwhile I will ask DDR expert for further help.

Jay Kaneria said:

Apart, from the above changes, I have generated the k3-am62Ax-ddr-config.dtsi from sysconfig tool and coping into k3-am62a-ddr-1866mhz-32bit.dtsi file. Am I coping into correct file?

Yes, this is correct.

Regards,
Aparna

Hi Aparna, 

Thank you for your response. 

Let us know once you have words from expert. We will receive the custom board next week. We want to make all the changes related to ddr configuration in this week. All the help will be much appreciated.

Regards,

Jay

Hi Aparna, 

Any update on this thread?

Regards,

Jay

Hi Aparna, 

Let us know once you have update on this thread.

Regards,

Jay

Hi Jay, currently there is no further update. Will get back with a response in the next working day.

Regards,
Aparna

Hi Aparna, 

We will receive the custom board tomorrow. Please can we have clarity on RAM configuration for AM62A7 EVK? If we don't have the clarity on this than we will be stuck in the board bring-up. 

Regards,

Jay

Hi Aparna, 

Any update on this thread?

Regards,

Jay

Hi Aparna, 

I did below changes on the EVK to configure the RAM to 1GB instead of 4GB. 

diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index 5f1bd32a755..331dd58a4b4 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -26,9 +26,8 @@

        memory@80000000 {
                device_type = "memory";
-               /* 4G RAM */
-               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000000 0x80000000>;
+               /* 1G RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
                bootph-pre-ram;
        };

diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index f727b5f8258..a045f5f21f8 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -30,9 +30,8 @@

        memory@80000000 {
                device_type = "memory";
-               /* 4G RAM */
-               reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000000 0x80000000>;
+               /* 1G RAM */
+               reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
        };

        reserved-memory {
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 732a9ede025..1e09a1b86ca 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -245,20 +245,14 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
        {
                .virt = 0x0UL,
                .phys = 0x0UL,
-               .size = 0x80000000UL,
+               .size = 0x40000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
        }, {
                .virt = 0x80000000UL,
                .phys = 0x80000000UL,
-               .size = 0x80000000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-                        PTE_BLOCK_INNER_SHARE
-       }, {
-               .virt = 0x880000000UL,
-               .phys = 0x880000000UL,
-               .size = 0x80000000UL,
+               .size = 0x40000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
                         PTE_BLOCK_INNER_SHARE
        }, {
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 45bbffada46..7147294d95d 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -3,10 +3,9 @@ CONFIG_ARCH_K3=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SPL_GPIO=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_BOARD_HAS_32K_RTC_CRYSTAL=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SOC_K3_AM62A7=y
 CONFIG_K3_ATF_LOAD_ADDR=0x9e780000

I wanted to replicate the 1GB scenario as custom board would have only 1GB RAM. So, I have configure 1 bank instead of 2. Also, I have changed "k3-am62a-ddr-1866mhz-32bit.dtsi" with the file generated from the SYSCONFIG(DDR Configuration).

I am getting below error when I boot the board.

U-Boot SPL 2023.04-gb0d717b732 (Dec 06 2023 - 15:11:45 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.8--v09.01.08 (Kool Koala)')
am62a_init: board_init_f done
SPL initial stack usage: 17040 bytes
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Trying to boot from MMC1
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.9(release):v2.9.0-614-gd7a7135d32-dirty
NOTICE:  BL31: Built : 09:34:15, Aug 24 2023

U-Boot SPL 2023.04-gb0d717b732 (Dec 06 2023 - 15:11:45 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.8--v09.01.08 (Kool Koala)')
am62a_init: board_init_f done
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Trying to boot from MMC1
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed
am62a_init: spl_boot_device: devstat = 0xcb bootmedia = 0x9 bootindex = 0
Authentication passed


U-Boot 2023.04-gb0d717b732 (Dec 06 2023 - 15:11:45 +0000)

SoC:   AM62AX SR1.0 HS-FS
Model: SICK Camera Board
DRAM:  1 GiB
"Synchronous Abort" handler, esr 0x96000005
elr: 00000000808699b0 lr : 00000000808699ac (reloc)
elr: 00000000bff499b0 lr : 00000000bff499ac
x0 : 0000000043000014 x1 : 00000000ffffffff
x2 : 0000000043000014 x3 : 00000000bde93298
x4 : 0000000000000000 x5 : 0000000000000000
x6 : 0000000000000000 x7 : 0000000043000000
x8 : 0000000000000002 x9 : 0000000000000008
x10: 000000000000028c x11: 00000000bde9313c
x12: 0000000000000244 x13: 00000000bde931fc
x14: 00000000bde93760 x15: 00000000bde93760
x16: 0000000080869b54 x17: 0000000000000000
x18: 00000000bde9fdc0 x19: 00000000bdea07f0
x20: 00000000bdea0750 x21: 00000000bffcd350
x22: 00000000bdea1f48 x23: 00000000bdea0210
x24: 00000000bffcbfa0 x25: 00000000bde93548
x26: 00000000bde96a70 x27: 00000000bff9cde0
x28: 00000000000032d4 x29: 00000000bde932f0

Code: aa0003f3 aa1403e0 97ff32fb b4000b00 (b9400002)
Resetting CPU ...

resetting ...
"Synchronous Abort" handler, esr 0x96000005
elr: 00000000808646c4 lr : 00000000808646bc (reloc)
elr: 00000000bff446c4 lr : 00000000bff446bc
x0 : 00000000bdea2420 x1 : 000000004a60d000
x2 : 00000000bff4469c x3 : 00000000bde93008
x4 : 0000000000000008 x5 : 000000000000002c
x6 : 00000000bdea21a0 x7 : 00000000000000f5
x8 : 00000000bde93760 x9 : 0000000000000008
x10: 0000000000001b6c x11: 00000000bde92f2c
x12: 0000000000001540 x13: 0000000000000000
x14: 00000000bde93760 x15: 0000000000000021
x16: 00000000bff4469c x17: 0000000000000000
x18: 00000000bde9fdc0 x19: 00000000bdea23b8
x20: 00000000bdea2600 x21: 00000000bdea2370
x22: 00000000bdea1f48 x23: 00000000bdea0210
x24: 00000000bffcbfa0 x25: 00000000bde93548
x26: 00000000bde96a70 x27: 00000000bff9cde0
x28: 00000000000032d4 x29: 00000000bde92f30

Code: f9400000 97ff452a f9400ab4 f9400e81 (b9400021)
Resetting CPU ...

resetting ...
"Synchronous Abort" handler, esr 0x96000005
elr: 00000000808646c4 lr : 00000000808646bc (reloc)
elr: 00000000bff446c4 lr : 00000000bff446bc
x0 : 00000000bdea2420 x1 : 000000004a60d000
x2 : 00000000bff4469c x3 : 00000000bde92cd0
x4 : 0000000000000009 x5 : 0000000000000008
x6 : 00000000bdea21a0 x7 : 000000000000000a
x8 : 00000000bde93760 x9 : 0000000000000008
x10: 0000000000001cec x11: 00000000bde92b0c
x12: 000000000001869f x13: 0000000000000000
x14: 00000000bde93760 x15: 0000000000000021
x16: 00000000bff4469c x17: 0000000000000000
x18: 00000000bde9fdc0 x19: 00000000bdea23b8
x20: 00000000bdea2600 x21: 00000000bdea2370
x22: 00000000bdea1f48 x23: 00000000bdea0210
x24: 00000000bffcbfa0 x25: 00000000bde93548
x26: 00000000bde96a70 x27: 00000000bff9cde0
x28: 00000000000032d4 x29: 00000000bde92c10

Code: f9400000 97ff452a f9400ab4 f9400e81 (b9400021)
Resetting CPU ...

resetting ...
"Synchronous Abort" handler, esr 0x96000005
elr: 00000000808646c4 lr : 00000000808646bc (reloc)
elr: 00000000bff446c4 lr : 00000000bff446bc
x0 : 00000000bdea2420 x1 : 000000004a60d000
x2 : 00000000bff4469c x3 : 00000000bde929b0
x4 : 0000000000000009 x5 : 0000000000000008
x6 : 00000000bdea21a0 x7 : 00000000000000f5
x8 : 0000000000000001 x9 : 0000000000000008
x10: 00000000ffffffd0 x11: 0000000000000010
x12: 000000000001869f x13: 0000000000000000
x14: 00000000bde93760 x15: 0000000000000021
x16: 00000000bff4469c x17: 0000000000000000
x18: 00000000bde9fdc0 x19: 00000000bdea23b8
x20: 00000000bdea2600 x21: 00000000bdea2370
x22: 00000000bdea1f48 x23: 00000000bdea0210
x24: 00000000bffcbfa0 x25: 00000000bde93548
x26: 00000000bde96a70 x27: 00000000bff9cde0
x28: 00000000000032d4 x29: 00000000bde928f0

Can you please help us on this?

Regards,

Jay 

Hello Jay,

The DDR expert has not reverted back yet. Apologies for delayed response.

What is the DDR part being used in your custom board?

I will try the same on my setup and let you know if your DDR configuration can be replicated.

Regards,
Aparna

Hi Aparna, 

Thank you for your reply. 

We are going to use Micron's DDR Part#: MT53E256M32D1KS-046 IT:L 

let me know if any other information is required. 

Regards,

Jay

Hi Aparna, 

Any update from the expert on this thread?

Regards,

Jay

Jay, can you send the .syscfg file from the DDR configuration tool in sysconfig.  I'd like to see what changes you made for 1GB.

Regards,

James

Hi James,

Please find the .syscfg file from sysconfig tool. 

// @cliArgs --device "AM62Ax" --package "AMB" --part "Default" --product "Processor_DDR_Config@0.10.02"

const DDRSS = scripting.addModule("/DDRSS");
DDRSS.system_cfg_dram_type = "LPDDR4";

DDRSS.lpddr4.config_fsp2_MHz = 1866;
DDRSS.lpddr4.system_cfg_temp_range = "-40C to 95C";
DDRSS.lpddr4.config_dram_mr3_dbi_rd_FS2 = "Disable";
DDRSS.lpddr4.config_dram_mr3_dbi_wr_FS2 = "Enable";
DDRSS.lpddr4.config_dram_mr2_rl_FS2 = 6;
DDRSS.lpddr4.config_dram_mr2_wls_FS2 = "WL set A";
DDRSS.lpddr4.config_dram_mr2_wl_FS2 = 4;
DDRSS.lpddr4.config_dram_mr1_nWR_FS2 = 6;
DDRSS.lpddr4.config_dram_odtlon_FS2 = 8;
DDRSS.lpddr4.config_dram_odtloff_FS2 = 28;
DDRSS.lpddr4.config_io_cell_enslicep_drv_dl0_dq = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicep_drv_ac = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_drv_dl0_dq = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_drv_ac = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicep_odt_dl0_dq = "Hi-Z";
DDRSS.lpddr4.config_io_cell_enslicen_odt_dl0_dq = "40 Ohm";
DDRSS.lpddr4.config_dram_byteswap_01 = "No";
DDRSS.lpddr4.config_dram_byteswap_23 = "No";

DDRSS.lpddr4.config_fsp0_MHz = 50;
DDRSS.lpddr4.config_fsp1_MHz = 1866;
DDRSS.lpddr4.system_cfg_dram_width = 32;
DDRSS.lpddr4.system_cfg_dram_density = 8;
DDRSS.lpddr4.system_cfg_dram_ranks = 1;
DDRSS.lpddr4.system_cfg_dram_mr4_poll = "No";
DDRSS.lpddr4.system_cfg_sys_temp_grad = 30;
DDRSS.lpddr4.config_dram_mr3_dbi_rd_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr3_dbi_rd_FS1 = "Disable";
DDRSS.lpddr4.config_dram_mr3_dbi_wr_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr3_dbi_wr_FS1 = "Enable";
DDRSS.lpddr4.system_cfg_lpm = "Yes";
DDRSS.lpddr4.system_cfg_fastboot = "No";
DDRSS.lpddr4.system_cfg_periodic_train = "Yes";
DDRSS.lpddr4.system_cfg_periodic_zqcal = "Disabled";
DDRSS.lpddr4.system_wdqs_control = "Enabled";
DDRSS.lpddr4.config_dram_mr1_bl_FS0 = "16 sequential";
DDRSS.lpddr4.config_dram_mr1_bl_FS1 = "16 sequential";
DDRSS.lpddr4.config_dram_mr1_bl_FS2 = "16 sequential";
DDRSS.lpddr4.config_dram_mr1_rd_pre_FS0 = "Static";
DDRSS.lpddr4.config_dram_mr1_rd_pre_FS1 = "Static";
DDRSS.lpddr4.config_dram_mr1_rd_pre_FS2 = "Static";
DDRSS.lpddr4.config_dram_mr1_rd_pst_FS0 = "0.5 x tCK";
DDRSS.lpddr4.config_dram_mr1_rd_pst_FS1 = "0.5 x tCK";
DDRSS.lpddr4.config_dram_mr1_rd_pst_FS2 = "0.5 x tCK";
DDRSS.lpddr4.config_dram_mr3_wr_pst_FS0 = "0.5 x tCK";
DDRSS.lpddr4.config_dram_mr3_wr_pst_FS1 = "0.5 x tCK";
DDRSS.lpddr4.config_dram_mr3_wr_pst_FS2 = "0.5 x tCK";
DDRSS.lpddr4.config_dram_mr2_rl_FS0 = 6;
DDRSS.lpddr4.config_dram_mr2_wls_FS0 = "WL set A";
DDRSS.lpddr4.config_dram_mr2_wl_FS0 = 4;
DDRSS.lpddr4.config_dram_mr1_nWR_FS0 = 6;
DDRSS.lpddr4.config_dram_odtlon_FS0 = 0;
DDRSS.lpddr4.config_dram_odtloff_FS0 = 0;
DDRSS.lpddr4.config_dram_mr2_rl_FS1 = 6;
DDRSS.lpddr4.config_dram_mr2_wls_FS1 = "WL set A";
DDRSS.lpddr4.config_dram_mr2_wl_FS1 = 4;
DDRSS.lpddr4.config_dram_mr1_nWR_FS1 = 6;
DDRSS.lpddr4.config_dram_odtlon_FS1 = 8;
DDRSS.lpddr4.config_dram_odtloff_FS1 = 28;
DDRSS.lpddr4.config_dram_tADR_ns = 20;
DDRSS.lpddr4.config_dram_tCAENT_ns = 250;
DDRSS.lpddr4.config_dram_tCCD_tCK = 8;
DDRSS.lpddr4.config_dram_tCCDMW_tCK = 32;
DDRSS.lpddr4.config_dram_tCKCKEH_ns = 1.75;
DDRSS.lpddr4.config_dram_tCKCKEH_tCK = 3;
DDRSS.lpddr4.config_dram_tCKE_ns = 7.5;
DDRSS.lpddr4.config_dram_tCKE_tCK = 4;
DDRSS.lpddr4.config_dram_tCKEHCS_ns = 7.5;
DDRSS.lpddr4.config_dram_tCKEHCS_tCK = 5;
DDRSS.lpddr4.config_dram_tCKEHDQS_ns = 10;
DDRSS.lpddr4.config_dram_tCKELCK_ns = 5;
DDRSS.lpddr4.config_dram_tCKELCK_tCK = 5;
DDRSS.lpddr4.config_dram_tCKELCS_ns = 5;
DDRSS.lpddr4.config_dram_tCKELCS_tCK = 5;
DDRSS.lpddr4.config_dram_tCKFSPE_ns = 7.5;
DDRSS.lpddr4.config_dram_tCKFSPE_tCK = 4;
DDRSS.lpddr4.config_dram_tCKFSPX_ns = 7.5;
DDRSS.lpddr4.config_dram_tCKFSPX_tCK = 4;
DDRSS.lpddr4.config_dram_tCMDCKE_ns = 1.75;
DDRSS.lpddr4.config_dram_tCMDCKE_tCK = 3;
DDRSS.lpddr4.config_dram_tCSCKE_ns = 1.75;
DDRSS.lpddr4.config_dram_tCSCKEH_ns = 1.75;
DDRSS.lpddr4.config_dram_tDQSCKmax_ns = 3.6;
DDRSS.lpddr4.config_dram_tDQSCKmin_ns = 1.5;
DDRSS.lpddr4.config_dram_tDStrain_ns = 2;
DDRSS.lpddr4.config_dram_tESCKE_ns = 1.75;
DDRSS.lpddr4.config_dram_tESCKE_tCK = 3;
DDRSS.lpddr4.config_dram_tFAW_ns = 40;
DDRSS.lpddr4.config_dram_tFAW_tCK = 0;
DDRSS.lpddr4.config_dram_tFClong_ns = 250;
DDRSS.lpddr4.config_dram_tINIT1_ns = 200000;
DDRSS.lpddr4.config_dram_tINIT2_ns = 10;
DDRSS.lpddr4.config_dram_tINIT3_ns = 2000000;
DDRSS.lpddr4.config_dram_tINIT4_tCK = 5;
DDRSS.lpddr4.config_dram_tINIT5_ns = 2000;
DDRSS.lpddr4.config_dram_tMRWCKEL_ns = 14;
DDRSS.lpddr4.config_dram_tMRWCKEL_tCK = 10;
DDRSS.lpddr4.config_dram_tMRD_ns = 14;
DDRSS.lpddr4.config_dram_tMRD_tCK = 10;
DDRSS.lpddr4.config_dram_tMRR_tCK = 8;
DDRSS.lpddr4.config_dram_tMRRI_tCK = 3;
DDRSS.lpddr4.config_dram_tMRW_ns = 10;
DDRSS.lpddr4.config_dram_tMRW_tCK = 10;
DDRSS.lpddr4.config_dram_tMRZ_ns = 1.5;
DDRSS.lpddr4.config_dram_tODToffMAX_ns = 3.5;
DDRSS.lpddr4.config_dram_tODToffMIN_ns = 1.5;
DDRSS.lpddr4.config_dram_tODTonMAX_ns = 3.5;
DDRSS.lpddr4.config_dram_tODTonMIN_ns = 1.5;
DDRSS.lpddr4.config_dram_tOSCO_ns = 40;
DDRSS.lpddr4.config_dram_tOSCO_tCK = 8;
DDRSS.lpddr4.config_dram_tPPD_tCK = 4;
DDRSS.lpddr4.UNREFERENCED = 100;
DDRSS.lpddr4.config_dram_tRASmax_ns = 8775;
DDRSS.lpddr4.config_dram_tRASmin_ns = 42;
DDRSS.lpddr4.config_dram_tRASmin_tCK = 3;
DDRSS.lpddr4.config_dram_tRCD_ns = 18;
DDRSS.lpddr4.config_dram_tRCD_tCK = 4;
DDRSS.lpddr4.config_dram_tREFIab_ns = 3906;
DDRSS.lpddr4.config_dram_tREFIpb_ns = 488;
DDRSS.lpddr4.config_dram_tRFCab_ns = 130;
DDRSS.lpddr4.config_dram_tRFCpb_ns = 60;
DDRSS.lpddr4.config_dram_tRPab_ns = 21;
DDRSS.lpddr4.config_dram_tRPab_tCK = 3;
DDRSS.lpddr4.config_dram_tRPpb_ns = 18;
DDRSS.lpddr4.config_dram_tRPpb_tCK = 3;
DDRSS.lpddr4.config_dram_tRRD_ns = 10;
DDRSS.lpddr4.config_dram_tRRD_tCK = 4;
DDRSS.lpddr4.config_dram_tRTP_ns = 7.5;
DDRSS.lpddr4.config_dram_tRTP_tCK = 8;
DDRSS.lpddr4.config_dram_tSDO_ns = 20;
DDRSS.lpddr4.config_dram_tSDO_tCK = 12;
DDRSS.lpddr4.config_dram_tSR_ns = 15;
DDRSS.lpddr4.config_dram_tSR_tCK = 3;
DDRSS.lpddr4.config_dram_TempMargin_ns = 2;
DDRSS.lpddr4.config_dram_tTSI_ns = 32000000;
DDRSS.lpddr4.config_dram_tVRCG_DISABLE_ns = 100;
DDRSS.lpddr4.config_dram_tVRCG_ENABLE_ns = 200;
DDRSS.lpddr4.config_dram_tVREFcalong_ns = 250;
DDRSS.lpddr4.config_dram_tVREFcashort_ns = 80;
DDRSS.lpddr4.config_dram_tWR_ns = 18;
DDRSS.lpddr4.config_dram_tWR_tCK = 4;
DDRSS.lpddr4.config_dram_tWTR_ns = 10;
DDRSS.lpddr4.config_dram_tWTR_tCK = 8;
DDRSS.lpddr4.config_dram_tXP_ns = 7.5;
DDRSS.lpddr4.config_dram_tXP_tCK = 5;
DDRSS.lpddr4.config_dram_tXSR_tCK = 2;
DDRSS.lpddr4.config_dram_tZQCAL_ns = 1000;
DDRSS.lpddr4.config_dram_tZQCKE_ns = 1.75;
DDRSS.lpddr4.config_dram_tZQCKE_tCK = 3;
DDRSS.lpddr4.config_dram_tZQLAT_ns = 30;
DDRSS.lpddr4.config_dram_tZQLAT_tCK = 8;
DDRSS.lpddr4.config_dram_tZQRESET_ns = 50;
DDRSS.lpddr4.config_dram_tZQRESET_tCK = 3;
DDRSS.lpddr4.config_io_cell_mode_dl0 = "Range 0";
DDRSS.lpddr4.config_io_cell_vrefsel_dl0 = 16.7;
DDRSS.lpddr4.config_io_cell_mode_ac = "Range 0";
DDRSS.lpddr4.config_io_cell_vrefsel_ac = 16.7;
DDRSS.lpddr4.config_io_cell_enslicep_drv_dl0_dqs = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicep_drv_cs = "80 Ohm";
DDRSS.lpddr4.config_io_cell_enslicep_drv_clock = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_drv_dl0_dqs = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_drv_cs = "80 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_drv_clock = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicep_odt_dl0_dqs = "Hi-Z";
DDRSS.lpddr4.config_io_cell_enslicen_odt_dl0_dqs = "40 Ohm";
DDRSS.lpddr4.config_dram_mr14_vr_dq_FS0 = "Range 0";
DDRSS.lpddr4.config_dram_mr14_vr_dq_FS1 = "Range 0";
DDRSS.lpddr4.config_dram_mr14_vr_dq_FS2 = "Range 0";
DDRSS.lpddr4.config_dram_mr14_vref_dq_FS0 = 27.2;
DDRSS.lpddr4.config_dram_mr14_vref_dq_FS1 = 27.2;
DDRSS.lpddr4.config_dram_mr14_vref_dq_FS2 = 27.2;
DDRSS.lpddr4.config_dram_mr12_vr_ca_FS0 = "Range 0";
DDRSS.lpddr4.config_dram_mr12_vr_ca_FS1 = "Range 0";
DDRSS.lpddr4.config_dram_mr12_vr_ca_FS2 = "Range 0";
DDRSS.lpddr4.config_dram_mr12_vref_ca_FS0 = 25.6;
DDRSS.lpddr4.config_dram_mr12_vref_ca_FS1 = 25.6;
DDRSS.lpddr4.config_dram_mr12_vref_ca_FS2 = 25.6;
DDRSS.lpddr4.config_dram_mr3_pdds_FS0 = "RZQ/6(40ohm)";
DDRSS.lpddr4.config_dram_mr3_pdds_FS1 = "RZQ/6(40ohm)";
DDRSS.lpddr4.config_dram_mr3_pdds_FS2 = "RZQ/6(40ohm)";
DDRSS.lpddr4.config_dram_mr3_pu_cal_FS0 = "VDDQ / 3";
DDRSS.lpddr4.config_dram_mr3_pu_cal_FS1 = "VDDQ / 3";
DDRSS.lpddr4.config_dram_mr3_pu_cal_FS2 = "VDDQ / 3";
DDRSS.lpddr4.config_dram_mr22_odtd_ca_FS0 = "ODT_CA Bond Pad";
DDRSS.lpddr4.config_dram_mr22_odtd_ca_FS1 = "ODT_CA Bond Pad";
DDRSS.lpddr4.config_dram_mr22_odtd_ca_FS2 = "ODT_CA Bond Pad";
DDRSS.lpddr4.config_dram_mr22_odte_ck_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr22_odte_ck_FS1 = "Disable";
DDRSS.lpddr4.config_dram_mr22_odte_ck_FS2 = "Disable";
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS1 = "Enable";
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS2 = "Enable";
DDRSS.lpddr4.config_dram_mr11_ca_odt_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr11_ca_odt_FS1 = "RZQ/5(48ohm)";
DDRSS.lpddr4.config_dram_mr11_ca_odt_FS2 = "RZQ/5(48ohm)";
DDRSS.lpddr4.config_dram_mr11_dq_odt_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr11_dq_odt_FS1 = "RZQ/5(48ohm)";
DDRSS.lpddr4.config_dram_mr11_dq_odt_FS2 = "RZQ/5(48ohm)";
DDRSS.lpddr4.config_dram_mr22_soc_odt_FS0 = "Disable";
DDRSS.lpddr4.config_dram_mr22_soc_odt_FS1 = "RZQ/6(40ohm)";
DDRSS.lpddr4.config_dram_mr22_soc_odt_FS2 = "RZQ/6(40ohm)";
DDRSS.lpddr4.config_dram_DQ0 = "Memory DQ0";
DDRSS.lpddr4.config_dram_DQ1 = "Memory DQ1";
DDRSS.lpddr4.config_dram_DQ2 = "Memory DQ2";
DDRSS.lpddr4.config_dram_DQ3 = "Memory DQ3";
DDRSS.lpddr4.config_dram_DQ4 = "Memory DQ4";
DDRSS.lpddr4.config_dram_DQ5 = "Memory DQ5";
DDRSS.lpddr4.config_dram_DQ6 = "Memory DQ6";
DDRSS.lpddr4.config_dram_DQ7 = "Memory DQ7";
DDRSS.lpddr4.config_dram_DM0 = "Memory DMI0";
DDRSS.lpddr4.config_dram_DQ8 = "Memory DQ8";
DDRSS.lpddr4.config_dram_DQ9 = "Memory DQ9";
DDRSS.lpddr4.config_dram_DQ10 = "Memory DQ10";
DDRSS.lpddr4.config_dram_DQ11 = "Memory DQ11";
DDRSS.lpddr4.config_dram_DQ12 = "Memory DQ12";
DDRSS.lpddr4.config_dram_DQ13 = "Memory DQ13";
DDRSS.lpddr4.config_dram_DQ14 = "Memory DQ14";
DDRSS.lpddr4.config_dram_DQ15 = "Memory DQ15";
DDRSS.lpddr4.config_dram_DM1 = "Memory DMI1";
DDRSS.lpddr4.config_dram_DQ16 = "Memory DQ16";
DDRSS.lpddr4.config_dram_DQ17 = "Memory DQ17";
DDRSS.lpddr4.config_dram_DQ18 = "Memory DQ18";
DDRSS.lpddr4.config_dram_DQ19 = "Memory DQ19";
DDRSS.lpddr4.config_dram_DQ20 = "Memory DQ20";
DDRSS.lpddr4.config_dram_DQ21 = "Memory DQ21";
DDRSS.lpddr4.config_dram_DQ22 = "Memory DQ22";
DDRSS.lpddr4.config_dram_DQ23 = "Memory DQ23";
DDRSS.lpddr4.config_dram_DM2 = "Memory DMI2";
DDRSS.lpddr4.config_dram_DQ24 = "Memory DQ24";
DDRSS.lpddr4.config_dram_DQ25 = "Memory DQ25";
DDRSS.lpddr4.config_dram_DQ26 = "Memory DQ26";
DDRSS.lpddr4.config_dram_DQ27 = "Memory DQ27";
DDRSS.lpddr4.config_dram_DQ28 = "Memory DQ28";
DDRSS.lpddr4.config_dram_DQ29 = "Memory DQ29";
DDRSS.lpddr4.config_dram_DQ30 = "Memory DQ30";
DDRSS.lpddr4.config_dram_DQ31 = "Memory DQ31";
DDRSS.lpddr4.config_dram_DM3 = "Memory DMI3";

Mainly I have changed "RANK" from 2 to 1 as our 1GB ddr has single RANK. Apart from that 2 or 3 timing parameter is changed as per DDR datasheet. Let me know if you need any other information.

Regards,

Jay

Hi Jay,

you have set DRAM density to 8?  is that correct?  The value should be "density per channel".  If you have a 1GByte device, wouldn't it be 4Gb per channel?

Regards,

James

Hi James,

Yes, We have DRAM density of 8Gb(1GB). DRAM we have used has single RANK. So, I believe we have 8Gb on single RANK. So, I have configured 8Gb instead 4Gb with 2 RANK.

Part number of our ddr is "MT53E256M32D1KS-046 IT:L". I am attaching datasheet of our custom DRAM for your reference. let me know that my understanding is correct or not? 

    memory@80000000 {
        device_type = "memory";
        /* 4G RAM */
        reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
              <0x00000008 0x80000000 0x00000000 0x80000000>;
    };

Where EVK is using DRAM with dual RANK configuration. So, EVK might be using 16Gb per channel(total 32Gb = 4GB). So, dts file of EVK containing two entry for DRAM configuration. Let me know if this understanding is correct or not.

Also, I have another question related to DFU. If i have DRAM changes, Do i need to do this changes in DFU image as well? Currently our custom board is stuck at tiboot3.bin. Board don't listen for tispl.bin when we are trying to flash using the DFU utility over USB interface. It will be great help if we get answer for DFU image for changed DRAM configuration.

Regards

Jay

Jay, the device you are using dual channel, single rank (4Gb per channel).  So you would need to change that in the configuration

I don't think the image changes based on the DRAM configuration.  Can you try with the above change.  I have not looked at the rest of the config changes yet, so let me know if you are still stuck

Regards,

James

Hi James,

JJD said:

Jay, the device you are using dual channel, single rank (4Gb per channel).  So you would need to change that in the configuration

Thank you for dual channel clarification. Apart from this, we had issue with DFU image as well.

We were having issue with DFU's default images (tiboot3.bin, tispl.bin, u-boot.img). We had to do the changes related to DRAM in DFU source as well and than we built DFU images again as mention here.

After that DFU images getting loaded in DRAM and started listing for final boot images and rootfs. And we were able to boot the our custom board successfully. So, we are good with booting board with 1GB RAM.

Question related to tiboot3.bin image compilation:

We are using the yocto project SDK for our final images. As I can see, my tiboot3.bin is not getting compiled once i do DRAM changes in u-boot source and build u-boot again. DRAM changes would be required in tiboot3.bin as well. right?

Currently, We have to build tiboot3.bin from processor SDK. So, Do you have idea that how can we build tiboot3.bin image from yocto project?

Regards,

Jay

Ok, good to know your DDR issues are resolved.  I'm will have to pass your question on to our software team.

regards,

James

Hello,

The yocto owner is out for the rest of September.

If you search the SDK docs you can find some basic information on yocto - not sure if it is enough to get you moving. You might also find useful information searching the forums:
https://software-dl.ti.com/processor-sdk-linux/esd/AM62AX/10_00_00/exports/docs/search.html?q=yocto&check_keywords=yes&area=default

Regards,

Nick

Hi Nick, 

Thank you for providing the reference. We have gone through the reference you have provided but didn't get any useful topic to compile tiboot3.bin. Let us know once Yocto owner is back.

Regards,

Jay