Part Number: AM6422
Tool/software:
Hi TI expert,
I have an emergent request, here's my usage schenario:
I config GPMC as a SRAM interface to transfer data with my FPGA. And actually I use DMA to read/write data from/to GPMC to local SRAM.
I config no CSDelay for successive access(please refer to my following timing setting), and I did see no CS deassert while do successive read via DMA, please refer to following screenshot.
Signals are: "re"(read enable), 'we'(write enable), 'cs'(chip select)
But for success write via DMA, CS pin got one cycle of deassert, I wonder that Is there a way to avoid it.
my timing setting is like following:
{
.gpmcBaseAddr = CSL_GPMC0_CFG_BASE,
.dataBaseAddr = CSL_GPMC0_DATA_BASE,
.elmBaseAddr = CSL_ELM0_BASE,
.inputClkFreq = 133333333U,
.intrNum = 138,
.intrPriority = 4U,
.chipSelBaseAddr = 1342177280U,
.chipSelAddrSize = GPMC_CS_MASK_ADDR_SIZE_16MB,
.clkDivider = CSL_GPMC_CONFIG1_GPMCFCLKDIVIDER_DIVBY1,
.waitPinNum = CSL_GPMC_CONFIG1_WAITPINSELECT_W0,
.addrDataMux = CSL_GPMC_CONFIG1_MUXADDDATA_NONMUX,
.timeLatency = CSL_GPMC_CONFIG1_TIMEPARAGRANULARITY_X1,
.waitPinPol = CSL_GPMC_CONFIG_WAIT0PINPOLARITY_W0ACTIVEL,
.readType = CSL_GPMC_CONFIG1_READTYPE_RDSYNC,
.writeType = CSL_GPMC_CONFIG1_WRITETYPE_WRSYNC,
.timingParams =
{
.csOnTime = 0U,
.csRdOffTime = 4U,
.csWrOffTime = 4U,
.advOnTime = 4U,
.advRdOffTime = 5U,
.advWrOffTime = 6U,
.advAadMuxOnTime = 1U,
.advAadMuxRdOffTime = 2U,
.advAadMuxWrOffTime = 2U,
.weOnTtime = 1U,
.weOffTime = 3U,
.oeOnTime = 1U,
.oeOffTime = 3U,
.oeAadMuxOnTime = 1U,
.oeAadMuxOffTime = 7U,
.pageBurstAccess = 0U,
.rdAccessTime = 3U,
.wrAcessTime = 2U,
.rdCycleTime = 4U,
.wrCycleTime = 4U,
.wrDataOnMuxBusTime = 0U,
.cycle2CycleDelay = 0U,
.busTurnAroundTime = 0U,
.cycleDelaySameChipSel = CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_NOC2CDELAY,
.cycleDelayDiffChipSel = CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY,
},
