• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 99 subscribers
  • Views 144 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

J784S4XEVM: TDA4VH

Mehmet Saglam
Prodigy 50 points
Part Number: J784S4XEVM

Tool/software:

I have a few questions about layout design of LPDDR4 RAM which is used at the J784S4X eval board(E4-4.6).

I made comparison of layout design of LPDDR4 RAM and instructions which are given at the Jacinto 7 LPDDR4 Board Design and Layout Guidelines application note file.

Questions are based on data group routing, CK and ADDR_CTRL routing specifications.

We are about the complete layout of our PCB, can you give us fast feedback?

 

  1. What kind of system level requirement should be defined to have less DQS propagation delay than CK pair? What kind of memory package calculations are done for this requirement? Can you give us an example?

DDR0_DQS0 and DDR0_DQS2 differential lines are longer than the CK pair for the U54 component at the eval board layout design. But, they should be shorter than the CK pair according to following requirement.

        2. Why propagation delay of each DQS pair must be less than propagation delay of DQ/DM?

When I checkout the length of DQS pairs for U54 component at the eval board, I observe that each DQS pair almost have the same length with corresponding BYTEx at the layout of J784S4X eval board.

In other words, propagation delay of DQS pairs is not shorter than DQ/DM lines.

        3. I have a question about length match of the ADDR_CTRL lines for the U54 component at the layout of J784S4X eval board. Why length match of DDR0_CA and DDR0_CKE lines is about 30 mil? I think it already exceeds 3ps skew time?,

I think that length of DDR0_CKE lines also should be 1330 mil.


        4. When I checked out the routing of DDR0_CK_C and DDR0_CK_T differential pair, they are also T-branch lines. At the T-branch point, routing is done with single ended impedance. According to PROC141E4_FAB document, single ended impedance value should be 66 ohm.  

PCB designers of the eval board used 3 mils trace width to accomplish 66-ohm single ended impedance. When I checked out the trace impedance of this line by using a software tool, I realized that line impedance is not 66-ohm, it is about 55-ohm.

I think that this impedance mismatch is really important for the clock signals.

They can still reach out 4266 Mbit/s data rate in this case? Did they test the maximum data rate of the RAM on the eval board?




  • 0
    TI__Guru 52525 points

    Question 1:  I don't understand question.  As stated in guidelines, the requirement is all DQS prop delay is less than prob delay of CK.  Yes - EVM violates this requirement by approx. 4ps.  Other EVM interfaces are within spec.

    Question 2:  As stated in guidelines, the requirement is DQS should have shortest prop delay of byte lanes.  Yes - EVM violates this requirement by max 2ps.

    Question 3:  The CA and CKE are slip into two different matching groups:

    Question 4:  It is recommended to route CK as different pair from beginning to end, including T-branch segments.  The impedance of the T-branch segments should be 2x the original trace impedance, but often that is not achievable.  Recommendation is to get as close to 2x impedance as PCB allows and run simulations to determine impact.  The EVM implementation does pass as maximum frequency.