Original question:
Tool/software:
We have been testing the new 10 SDK and have just noticed this clock error. We see that it was a problem in the 9.2 sdk (see this e2e post: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1328959/am625-ti-sci-clk-recalc-rate-errors/5081170).
My question is: How can we fix this?
Thank you,
Joshua Bourgeot
Hello Joshua,
Looks like this was not filed in time to get into SDK 10.0, but we do have a bug filed to fix for SDK 10.1. It looks like the person who wrote the code for AM62x PRUSS just copy-pasted the clock settings from AM64x PRU_ICSSG, without taking into account the fact that the AM62x clock tree is different.
Ok, so how to fix it?
That requires a longer discussion.
Since these settings were copied from AM64x, let's first figure out what is going on with AM64x:
In the default AM64x settings, the interface clock (iclk) sources the VCLK input (i.e., iclk = VCLK):
And we can verify from the AM64x TISCI clocks that clock ID 20 = VCLK = iclk = 250MHz
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am64x/clocks.html#clocks-for-pru-icssg0-device
What if we want to do the same thing on AM62x? Can we just find the VCLK entry and set the clock source to that?
No. Or at least, I don't think so.
First off, I strongly suspect that the AM62x TRM graphic on the PRU's clock generation is WRONG. i.e., I believe this diagram and paragraph are NOT CORRECT. I will file a bug against the TRM to make sure:
Here's what we know for sure:
The clock going to the AM62x PRU cores can be sourced from either MAIN_PLL2_HSDIV0_CLKOUT, or MAIN_PLL_HSDIV9_CLKOUT. From the TRM's module integration chapter:
Here's what I don't know:
AM64x had several additional clocking options (e.g., send VCLK input to CORE_CLK and IEP_CLK so that IEP counter & core counter are synchronous with the interface clock, route IEP_CLK input to the CORE_CLK). I do not see any evidence that those clocking options also exist on AM62x, but I will check.
Note the devicetree's addresses here for both AM64x & AM62x:
pruss_cfg: cfg@26000 refers to the PRU CFG registers at offset 0x2_6000 from the beginning of the PRU register set
coreclk-mux@3c refers to the CFG register at 0x3C. On AM64x, this register selects the CORE_CLK source between ICSSGn_CORE_CLK and ICLK/VCLK.
I don't know what that register does on AM62x (if anything). If it still selects between CORE_CLK and VCLK, that behavior is undocumented.
ok, so... what next?
Are you actually using the PRU subsystem, or are you just trying to squash any error outputs during boot time?
If you are using the PRU subsystem, what frequency do you want to run the PRU cores at? "standard" options are 200MHz, 250MHz, 333MHz (5ns, 4ns, 3ns per clock cycle)
I suspect we'll need to do "multiple levels of clock muxing" as described here for AM64x, but I don't know for sure since I haven't tried on AM62x yet:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1049800/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-linux
Regards,
Nick
Partial update for any future customers:
Rev B of AM62x TRM is wrong. The PRU subsystem in AM62x has the same input clock configuration as AM64x:
And the mux for CORE_CLK input and IEP_CLK input is still controlled by the same registers as AM64x:
ICSSG_IEPCLK_REG (offset 0x26000, register 0x30)
Bit IEP_OCP_CLK_EN: 0h = iep_clk is the source, 1h = ICSSGn_CORE_CLK is the source
ICSSG_CORE_SYNC_REG (offset 0x26000, register 0x3C)
Bit CORE_VBUSP_SYNC_EN: 0h = ICSSGn_CORE_CLK is the source, 1h = ICSSGn_ICLK is the source
Note that the PRU core frequency (CORE_CLK) can be sourced by either the external CORE_CLK input, or the VCLK (i.e., interface clock) input, but NOT the IEP_CLK input. The paragraph in the image above says that the "CORE block" allows software to select from the IEP_CLK, but it looks like "CORE block" (which includes IEP_CLK, CORE_CLK, and VCLK) is different from "PRU core" (which is CORE_CLK).
Regards,
Nick
