HI,
Does anyone know the particulars about setting the EMIF regs on the EZDSP to minimize the access time to the onboard flash memory. I have some LUT's in the flash memory way above the boot image. The registers: ACS2CR1, ACS2CR@, AWCCR1, AWCCR2 are of concern. I beleive the flash has a 70nsec read cycle. The registers seem to default to a very long cycle. I guess I don;t know if it is normal or strobe mode. One would think they would use the wait state line shown ib the ezdsp schematic. It seems to me that they program one of the AWWxx regs with an 0x00E4 (in nor_write anyway). This seems to 'connect' the CS2 access to an external wait state pin that is grounded. Not the wired EMWAIt2. So i'm l;ooking for the proper config values to let me access this flash close to 70nsec. I've tried poking some strobe width values but the code composer seems set it back to something 'large'. ANy help? Thanks
SV
