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C6678 DDR3 simulation models

nonos
Prodigy 90 points
Other Parts Discussed in Thread: TMS320C6678

Hello,

I would like to do simulation of DDR3 interface for our designing C6678 board.
Now, I'm checking IBIS file of C6678 and found many models for this interface.

Regarding TX model for address and data line, I think **ohms mean setting of driver strength(resister which is connected between PTV15 and GND).
Our board is based on EVM, so we will use 45.3ohms.
In this case, should we use "TX 45ohms ..." model?

Regarding RX model for address and data line, some termination models are defined.
I'm not sure what this termination means.
(ODT or external termination?)
Could you explain about these termination settings?

Thanks,

  • 0
    TI__Mastermind 42545 points

    Based on your input you should be using the 9mA 45ohm TX model as defined by your 45.3ohm resistor.  You will have to pick the slew rate speed for that model based on your DDR3SLRATE[1:0] settings.  These values are defined as the following.

    DDR3SLRATE[1:0] = 00   Fastest

    DDR3SLRATE[1:0] = 01   Fast

    DDR3SLRATE[1:0] = 10   Slow

    DDR3SLRATE[1:0] = 11   Slowest

    For the RX model please use the RX mode 45ohm with full termination.  This is set as the default in the DDR3 configuration and presently we ask you not to change that value.

  • 0 in reply to Bill Taboada
    Intellectual 760 points

    Hi Bill,

    Not sure you've got the order right.  I remembered that the bit order from Fastest to Slowest was counter-intuitive.

    The H/W design guide has:

    Unless the h/w design guide is wrong of course.

    Richard.

  • 0 in reply to Richard Marsh
    TI__Mastermind 42545 points

    Hi Richard,

    The table in the Hardware Design Guide is incorrect.  It should be as follows.

    With Regards, Bill

     

    Table 18           Slew Rate Control

    Setting

    Speed

    DDRSLRATE1

    DDRSLRATE0

    00

    Fastest

    pulldown

    pulldown

    01

    Fast

    pulldown

    pullup

    10

    Slow

    pullup

    pulldown

    11

    Slowest

    pullup

    pullup

     

  • 0 in reply to Bill Taboada
    Expert 1985 points

    Hi Richard ,

    We observe that in the TMS320C6678 EVM board the slew rate is set to Slow if we go by your settings. Please confirm.

    Also , how do we configure the drive strength of DDR controller ? From IBIS models we observe that the drive strength can be varied from 8-10 mA. But we dont see any configuration register to set these values. In the SDRAM configuration register (SDCFG) there is a field to set the drive strength , but it is specified in terms of RZQ . How do we map this to the current value ?

    -Khader