Problem about DDR3 software config

Hello,

By writing to the above registers DDR controller starts initialization. If the leveling does not complete, you can see the hang issue. The following could be reasons for why the leveling is not completing.

1. The controller values are not set correctly for the targeted memory

2. Signals connectivity issue or clocks crossed or some kind of assembly issue.

Regards,
Marc

Hello,

I also got this matter, 4pcs board are failed, another 4pcs are ok. Using dvr_netra.gel and also found the same code cause failed:

if(DDR3) {
    /*  setup a small refresh period */
    WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x0000613B);   /* initially a large refresh period */
    WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x1000613B);   /* trigger initialization           */
    WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, (0x10000000|SDREF));   /* move to a smaller more correct one */
  if(TWO_EMIF){
     /*  setup a small refresh period */
     WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x0000613B);   /* initially a large refresh period */
     WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x1000613B);   /* trigger initialization           */
     WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, (0x10000000|SDREF));   /* move to a smaller more correct one */
 }

CCS Console output:

CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)

or

CortexA8: Trouble Writing Memory Block at 0x4d000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4D000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Release 5.0.333.0)

2pcs board are failed in DDR controller 0(EMIF4_0_SDRAM_REF_CTRL)

2pcs board are failed in DDR controller 1(EMIF4_1_SDRAM_REF_CTRL)

My board use 8pcs DDR3-1333( 2Gb per chip ) and memory chip is K4B2G0846C-HCH9.

CPU is C6A8168 or DM8168.

i just reconfig the follow registers for our DDR3 chip according to TMS320DM816x TRM DDR2/DDR3 Memory Controller description

#define EMIF4_0_SDRAM_CONFIG     (EMIF4_0_CFG_BASE_ADDR + 0x08)
#define EMIF4_0_SDRAM_REF_CTRL     (EMIF4_0_CFG_BASE_ADDR + 0x10)
#define EMIF4_0_SDRAM_TIM_1      (EMIF4_0_CFG_BASE_ADDR + 0x18)
#define EMIF4_0_SDRAM_TIM_2      (EMIF4_0_CFG_BASE_ADDR + 0x20)
#define EMIF4_0_SDRAM_TIM_3      (EMIF4_0_CFG_BASE_ADDR + 0x28)
#define EMIF4_0_DDR_PHY_CTRL_1     (EMIF4_0_CFG_BASE_ADDR + 0xE4)

but it still does't work.

Hello Garth,

I am facing the same issue, you have mentioned.

The only difference is the CPU, Its TMS320DM8168ACYG2

I am facing the problem in two boards.

Did you get it solved the problem?

Your help will be very useful for me.

Ankit..

Hi All,

I got the same problem. I use DM8167 and 4x MT41J128M16-125, 2 RAM on each EMIF. 

I have set SDRAM_TIM 1-3, SDRAM_CONFIG and SDRAM_REF according to Micron's datasheet.

#define EMIF_TIM1_DDR3_796 0x1557b9b5
#define EMIF_TIM2_DDR3_796 0x40877feb
#define EMIF_TIM3_DDR3_796 0x001f87ff
#define EMIF_SDREF_DDR3_796 0x10001844
#define EMIF_SDCFG_DDR3_796 0x6aa40b33
#define EMIF_PHYCFG_DDR3_796 0x0010010a

Tried 400MHz and 796.5MHz but both fail with same error:

CortexA8: Output: Device type is GP
CortexA8: Output: DM816x Main PLL Init is in Progress, Please wait .....
CortexA8: Output: DM816x Main PLL Init is Done .....
CortexA8: Output: DM816x DDR PLL Init is in Progress for 796.5 MHz DDR Clock, Please wait .....
CortexA8: Output: DM816x DDR PLL Init is Done .....
CortexA8: Output: DM816x DDR2/3 PRCM Init is in progress .....
CortexA8: Output: DM816x DDR2/3 PRCM Init is Done .....
CortexA8: Output: EMIF4P_Init .....
CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.791.0)
DDR3_796MHZ_doall() cannot be evaluated.
target access failed

Anyone have encounter this problem please help, thanks in advance.

Best Regards,

Mike

Haven't seen any solutions to this yet, has anyone been able to move past this?  We are having the exact same issue with a custom board using 2 MT41K256M16HA-125 IT:E chips per EMIF as well.  Any help would be appreciated!

Thanks in advance,

Adam

Hi Adam,

Your issue looks similar to this one:

http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/791/p/191233/724669.aspx

Best Regards,

Pavel

Thanks Pavel.  Yes, that helped! We also found that there's a bunch of configuration down toward the bottom of the DM816x.gel file we were using which needed to be filled in.  All the software leveling info (write DQS ratio, write data ratio, read DQS ratio, DQS gate timing, etc.).  It's unfortunate all the configuration info isn't organized neatly at the top, but once we got it all filled out our DDR started working again.  Hopefully this will help someone else also missing that info.

Thanks for the help!!

-ADam