AM3352: Impact when only VDD_MPU is OPP50 (0.95V)

Hello Daisuke

Thank you for the query.

Daisuke Maeda said:

Our customer has encountered an error when the power supply voltages are set for AM3352BZCZ30 as follows:

Please add more datails.

Daisuke Maeda said:

Are functions other than the ARM (A8) core also affected and limited when only VDD_MPU is OPP50 (0.95V)?

Refer below section of the data sheet 

Table 5-7. VDD_MPU OPPs for ZCZ Package With Device Revision Code "A" or Newer(1)

Help me understand what you meant by also?

I suspect the below is valid for any supply. 

7.3 OPP50 Support

Let me check.

Refer below for the allowed OPP combinations.

Table 5-8. Valid Combinations of VDD_CORE and VDD_MPU OPPs for ZCZ Package With Device Revision Code "A" or Newer

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your reply.

I have checked tables 5-6, 5-7, and 5-8 in the datasheet and confirmed that our customer meets the requirements.

Our customer is using under the following conditions:

VDD_CORE: 1.1V (OPP100)
VDD_MPU: 0.95V (OPP50)
ARM (A8): 300MHz (OPP50)

Are functions other than the ARM (A8) MPU Subsystem affected and limited under the above conditions?

Do the limitations in "7.3 OPP50 Support" on the datasheet apply under the above conditions?

Since VDD_CORE is 1.1V (OPP100), functions other than ARM (A8) MPU Subsystem should not be limited, but the datasheet does not make this clear.

Best regards,

Daisuke

Hello Daisuke

Thank you.

Kallikuppa Sreenivasa said:

Our customer has encountered an error when the power supply voltages are set for AM3352BZCZ30 as follows:

Please add more datails.

Please add additional inputs on the issue seen by customer.

Is the issue seen inline with the data sheet section related to OPP50 ?

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your reply.

Our customer is using a 3rd party RTOS and saw what appeared to be exceptions such as data abort and prefetch abort on the A8 core. They saw it on some of the same custom boards.

By the way, they changed VDD_MPU from 1.1V to 0.95V after power-up and always use AM3352BZCZ30 under the following conditions:

VDD_CORE: 1.1V (OPP100)
VDD_MPU: 0.95V (OPP50)

ARM (A8), MPU PLL (CLKOUT): 300MHz (OPP50)
Core PLL (CORE_CLKOUTM4, L3F_CLK, L4F_CLK): 200MHz (OPP100)
Core PLL (L3S_CLK, L4_PER, L4_WKUP): 100MHz (OPP100)
CORE_CLKOUTM5: 250MHz (OPP100)
CORE_CLKOUTM6: 500MHz (OPP100)
DDR3, DDR PLL (CLKOUT): 400MHz (OPP100)
CPSW: Used (Not supported in OPP50)
MDIO: Used (Not supported in OPP50)

Are the above conditions acceptable? Is normal operation possible when VDD_MPU is 0.95V (OPP50)?

Best regards,

Daisuke

Hello Daisuke

Thank you.

With the above changes, is the customer board functioning as expected or are they still seeing some issues ?

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your reply.

No changes to the conditions. The above conditions indicate the detailed conditions when the issues was saw.

Best regards,

Daisuke

Hello Daisuke

Thank you.

Let me check internally and update.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your support. Our customer is waiting for your reply.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hello Daisuke

Thank you for the follow-up.

I am following internally for an answer and will update at the earliest when i hear back from the expert,

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your support. Our customer is waiting for your reply.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hello Daisuke

Thank you for the follow-up.

The expert is on vacation this week.

I will follow-up early next week and update.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your support. Our customer is waiting for your update.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hello Daisuke

Thank you for the follow-up.

I am checking.

In the meantime, i did get a chance to talk to one of the design team member.

https://www.ti.com/lit/an/sprac74a/sprac74a.pdf

OPP Summary

7.3 OPP50 Support section in the data sheet could be for VDD_CORE OPP50.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your support. Our customer expects accurate answers.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hello Daisuke

Thank you.

Daisuke Maeda said:

Thank you for your support. Our customer expects accurate answers.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Understand. I am checking.

Regards,

Sreenivasa

Hi Sreenivasa-san,

Thank you for your reply.

Daisuke Maeda said:

Our customer is using a 3rd party RTOS and saw what appeared to be exceptions such as data abort and prefetch abort on the A8 core. They saw it on some of the same custom boards.

I suggested to our customer to check if there is any problem with accessing the RAM (On-Chip or DDR).

Best regards,

Daisuke

Hello Daisuke

Thank you.

Please also suggest customer to ensure all the recommended caps as per the data sheet for all the supply rails are provided.

Regards,

Sreenivasa