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uPP receive problem

Other Parts Discussed in Thread: OMAPL138

Hello,

I am using the uPP on an OMAPL138 to communicate to an FPGA, chan A xmit to FPGA and chan B rcv from the FPGA.  I am writing my own driver in linux and have tested the driver in digital loopback mode.  When I configure the uPP again, not in digital loopback mode I see no data coming in from the fpga.  In my setup when I write some data to the FPGA on channel A I expect a response on Channel B. 

I have brought out the Enable, Start, Wait and clock signals for both channels to GPIO on the fpga.  When I write data out I see the start and enable go high going into the FPGA.  I then see the enable and start lines go high for data coming back into the OMAP.  Upon checking the UPQSx registers I see the rx_buf pointer has not updated and that the DMA is active.  Does the DMA active mean it is waiting on data to fulfill the DMA descriptors that were programmed?

thanks in advance, Scott

  • Scott,

    Sorry for the delay in responding.  I want to check that the FPGA (or transmit channel) is driving a clock to the receive channel's clock pin.  That signal is only generated by the uPP peripheral in transmit mode.  Since you are using uPP in duplex mode, the easiest way to get a receive clock is probably to connect the uPP clock pins together directly.

    Please let me know if you are still experiencing trouble with your driver.