Hi,
Where can I find more details about HD and VD Signal timings of DM643x VPFE peripheral.
Couldn't find the details in the user guide.
We would like know the below details in particular.
- How much blanking clock cycles are required between the 1st VD rising edge to
1st Line of HD rising edg. Will there be any problem if both start at same time?
- Similarly, how much blanking clock cycles required between,
last line of HD falling edge to VD falling edge.
Regards.
Mudigere.