Hello,
I'm having a problem where my high resolution timer is telling me that the DM3730 c64+ core is running at a higher rate than configured through the DPLL2 registers.
I'm running the DM3730 with an input clock of 26Mz (sys_xtalin). This is divided down to 13MHz using PRCM.PRM_CLKSRC_CTRL[7:6] to create input reference clocks for DPLL1 and DPLL2 modules that generate clocks for the MPU and DSP respectively. Both DPLL1 and DPLL2 are in locked mode, PRCM.CM_CLKEN_PLL_MPU[2:0] = 0x7 and PRCM.CM_CLKEN_PLL_IVA2[2:0] = 0x7 so use these 13MHz DPLL1_ALWON_FCLK and DPLL2_ALWON_FCLK clocks as input.
The C64+ core operating IVA2_CLK, calculated as (DPLL2_ALWON_FCLK * 2 * M)/(2 * (N+1) * M2) should be 544MHz. (M = PRCM.CM_CLKSEL1_PLL_IVA2[18:8] = 544, N = PRCM.CM_CLKSEL1_PLL_IVA2[6:0] = 12, M2 = PRCM.CM_CLKSEL2_PLL_IVA2[4:0] = 1). When I examine the DSPBIOS (5.41.07.24) high resolution timer however, the count (i.e. the C64+ TSCL register) is cycling at 800MHz, so doesn't match the calculated IVA2_CLK frequency.
Should the DPLL2 values always reflect the current c64+ core frequency or is there something else on the DM3730 system that could be overruling them? Can anyone see what I have missed?
Derrick Rea
P.S. I've captured all the PRCM register values at run-time using a JTAG debugger. VDD_MPU_IVA = 1.352 volts and SMARTFLEX is enabled, meaning that the device is running in the OPP1G operating performance point. MPU_CLK is running at 1GHz through the same set of calculations as above but applied
to DPLL1.