DRA821U-Q1: Not Seeing ECC Enable Printout in bootlogs on EVM

Hi Lewis,

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1381820/dra821u-q1-enabling-in-line-ecc-for-lpddr4-on-dra821---sdk9-02/5303319#5303319

Can you share the logs with the changes shared in the above e2e?

Can you please try with the evm before migrating to custom board?

Best regards,

Keerthy 

Hi Keerthy,

Here's what was output on the bootlogs on the EVM when following the changes in the other E2E thread; we're not seeing any indication of ECC being enabled like how you had it in the previous thread:

Lewis,

Okay. Are you trying on the same 9.2 SDK or have you migrated to 10.0 SDK? I haven't tried the inline ecc on 10.0 SDK.

Best regards,

Keerthy 

Keerthy,

This is on SDK 9.2, we haven't moved to SDK 10.0.

Regards,

Lewis

Hi Lewis,

Just double confirming that I tried again on 9.2 SDK with TI J7200_EVM. Changes below:

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 2e1c26d6..fd523221 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -63,6 +63,7 @@
        power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
                        <&k3_pds 90 TI_SCI_PD_SHARED>;
        clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
+       ti,ecc-enable;
 };
 
 &cbass_mcu_wakeup {
diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi
index 3a9ea42f..e9829077 100644
--- a/arch/arm/dts/k3-j721e-ddr.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr.dtsi
@@ -7,8 +7,9 @@
        memorycontroller: memorycontroller@0298e000 {
                compatible = "ti,j721e-ddrss";
                reg = <0x0 0x02990000 0x0 0x4000>,
-                     <0x0 0x0114000 0x0 0x100>;
-               reg-names = "cfg", "ctrl_mmr_lp4";
+                     <0x0 0x0114000 0x0 0x100>,
+                       <0x0 0x02980000 0x0 0x200>;
+               reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
                power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
                        <&k3_pds 90 TI_SCI_PD_SHARED>;
                clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 313c1cb0..55a22af0 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -120,6 +120,8 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
        detect_enable_hyperflash(spl_image->fdt_addr);
+       if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
+               fixup_ddr_driver_for_ecc(spl_image);
 }
 #endif
 
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 56b134ae..8f6297d6 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -177,3 +177,4 @@ CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_LIB_RATIONAL=y
 CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_K3_INLINE_ECC=y

Traces:

U-Boot SPL 2023.04-dirty (Sep 24 2024 - 07:48:23 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
ECC is enabled, priming DDR which will take several seconds.
ECC: priming DDR completed in 1865 msec
Trying to boot from MMC2
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE: BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE: BL31: Built : 16:09:05, Feb 9 2024
ERROR: Failed to get response (-19)
ERROR: Transfer send failed (-19)
ERROR: Unable to query firmware capabilities (-19)
I/TC:
I/TC: OP-TEE version: 4.1.0-51-g012cdca49 (gcc version 11.4.0 (GCC)) #1 Tue Jan 30 10:48:03 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2023.04-dirty (Sep 24 2024 - 07:48:17 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
Detected: J7X-BASE-CPB rev E3
Detected: J7X-GESI-EXP rev E3
Detected: J7X-VSC8514-ETH rev E2
Trying to boot from MMC2
am654_sdhci mmc@4fb0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted

U-Boot 2023.04-dirty (Sep 24 2024 - 07:48:17 +0530)

SoC: J7200 SR1.0 GP
Model: Texas Instruments K3 J7200 SoC
Board: J7200X-PM2-SOM rev E6
DRAM: 2 GiB (effective 4 GiB)
Core: 85 devices, 32 uclasses, devicetree: separate
Flash: 0 Bytes
MMC: mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In: serial@2800000
Out: serial@2800000
Err: serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
Detected: J7X-BASE-CPB rev E3
Detected: J7X-GESI-EXP rev E3
Detected: J7X-VSC8514-ETH rev E2
Net: eth0: ethernet@46000000port@1
Hit any key to stop autoboot: 0

If you have custom board configs then this will need more changes.

- Keerthy

Hey Keerthy,

Just checked our code and we have already implemented all those changes already. We are still not seeing the printout that says ECC is enabled, priming DDR which will take several seconds. ECC: priming DDR completed in 1865 msec.

Looking that the bootlogs you shared, it looks like the that bootlog printout occurs after tiboot3.bin. Is that correct? If so, we currently do not have visibility to see that on our EVM. Is there a way for us to see the bootlogs right after tiboot3.bin? Can you share how you are able acquire the bootlogs from the EVM with your setup.

Regards,

Lewis

Hi Lewis,

All of the inline ecc is implemented as part of tiboot3.bin. You can search for that print in drivers/ folder of the U-Boot repo. You can add debug prints around that code to check if it's indeed getting called in your case. Please double confirm if the config option is enabled.

Best regards,

Keerthy 

Hi Keerthy, 

Both myself and Lewis have double checked that the config option is enabled and that the tiboot3.bin file is being changed as instructed. Debug prints will not work since we cannot see any serial output at that time. We are planning on seeing if we can view the debug prints via Putty but hoping you can explain what else may be causing the logs to not output as expected. 

It may be easier to hop on a quick call to talk through what steps have been taken and make sure everyone is on the same page...

Thanks,

Luke

Luke,

Can you first try the SD card boot mode on EVM. Copy tiboot3.bin, tispl.bin, u-boot.img on to boot partition of the SD card and boot with the above patch.

- Keerthy

Hi Keerthy, 

I have attempted the SD card boot mode on the EVM and copied the files you mentioned over with the patches made as specified above and am not getting any different results. I am waiting to hear back from Lewis and team to see if they have had any success trying this.

Thanks,

Luke