PROCESSOR-SDK-J784S4: Understanding .L2 cache and more

Hi Joe,

Can you clarify what C7x core you are using? For example, in your post are you indexing with C7x1 being the first core of the device (up to C7x4)?

If you are referring to the first core, that would be the wrong L2RAM address for it. It looks like you are using the L2RAM address for C7x2

Refer to the system memory map that it's in vision_apps/platform/j784s4/rtos/system_memory_map.html

Can you try using 0x64800000?

Best,

Asha

Yeah, that first line was a typo. It should have been 0x64800000. We tried using this chart with no avail.

Here is some additional info. This is the Linux output. Not that we are not running any other cores.

Failed to load '/lib/firmware/j784s4-mcu-r5f0_1-fw'
Failed to load '/lib/firmware/j784s4-main-r5f0_0-fw'
Failed to load '/lib/firmware/j784s4-main-r5f0_1-fw'
Failed to load '/lib/firmware/j784s4-main-r5f1_0-fw'
Failed to load '/lib/firmware/j784s4-main-r5f1_1-fw'
Failed to load '/lib/firmware/j784s4-main-r5f2_0-fw'
Failed to load '/lib/firmware/j784s4-main-r5f2_1-fw'
wtx loaded /lib/firmware/j784s4-c71_0-fw @ 0x0000000082000000: 10815944 bytes read in 477 ms (21.6 MiB/s)
Warning: Did not detect image signing certificate. Skipping authentication to prevent boot failure. This will fail on Security Enforcing(HS-SE) devices
"Error" handler, esr 0xbf000000
elr: 00000000808bed18 lr : 000000008086e388 (reloc)
elr: 00000000fff84d18 lr : 00000000fff34388
x0 : 0000000064e00000 x1 : 0000000000000000
x2 : 0000000000001800 x3 : 0000000000000140
x4 : 0000000000000000 x5 : 00000000000016c0
x6 : 0000000000000000 x7 : 0000000000e0c000
x8 : 0000000000000010 x9 : 0000000000000008
x10: 0000000000000008 x11: 00000000fde969e0
x12: 0000000000000000 x13: 0000000000000200
x14: 0000000000000004 x15: 0000000000000020
x16: 00000000fff2f854 x17: 0000000000000000
x18: 00000000fde85db0 x19: 0000000000000000
x20: 0000000082a4fbf0 x21: 0000000000000000
x22: 0000000082000000 x23: 00000000fde8a2c0
x24: 00000000fff8f3b8 x25: 0000000000000000
x26: 0000000064e00000 x27: 0000000000001800
x28: 0000000064e00000 x29: 00000000fde6f630

Code: d2800004 eb04005f 540000e1 d65f03c0 (f8236804)
Resetting CPU ...

resetting ...

Hi Joe,

If you are trying to boot with the loadable segments within the C7x L2SRAM, this is not a supported configuration. C7x L2RAM can only be used as scratch memory and not for any loadable program/data segments.

Best,

Asha

Hi Asha,

Since Joe and I are working together on this issue, I thought I’d respond here. We have a PDK application developed on PSDK-RTOS-J784s4-09_02_00_05, where we are linking FFTLIB with our application. Below is the linker_c7x_freertos.cmd file that we use for our test application.

--ram_model
-heap  0x20000
-stack 0x20000
--args 0x1000
--diag_suppress=10068 /* "no matching section" */
--cinit_compression=off
-e _c_int00_secure

MEMORY
{
    L2SRAM (RWX):   org = 0x64800000, len = 0x00070000
    L1DSRAM  (RWX): org = 0x64E00000, len = 0x004000   // 16kB, for J7
    MSMCSRAM (RWX): org = 0x70000100, len = 0x7fff00
}

SECTIONS
{
    boot:
    {
      boot.*<boot.oe71>(.text)
    } load > C7X_1_TEXT ALIGN(0x200000)
    .vecs       >       C7X_1_DDR_SPACE ALIGN(0x400000)
    .secure_vecs    >   C7X_1_DDR_SPACE ALIGN(0x200000)
    .text:_c_int00_secure > C7X_1_DDR_SPACE ALIGN(0x200000)
    .text       >       C7X_1_DDR_SPACE ALIGN(0x200000)

    .l1dmemory  >       L1DSRAM
    .l2dmemory  >       L2SRAM
    .bss        >       C7X_1_DDR_SPACE  /* Zero-initialized data */
    .data       >       C7X_1_DDR_SPACE  /* Initialized data */

    .cinit      >       C7X_1_DDR_SPACE  /* could be part of const */
    .init_array >       C7X_1_DDR_SPACE  /* C++ initializations */
    .stack      >       C7X_1_DDR_SPACE ALIGN(0x2000)
    .args       >       C7X_1_DDR_SPACE
    .cio        >       C7X_1_DDR_SPACE
    .const      >       C7X_1_DDR_SPACE
    .switch     >       C7X_1_DDR_SPACE /* For exception handling. */
    .sysmem     >       C7X_1_DDR_SPACE /* heap */

    GROUP:              >  C7X_1_DDR_SPACE
    {
        .data.Mmu_tableArray          : type=NOINIT
        .data.Mmu_tableArraySlot      : type=NOINIT
        .data.Mmu_level1Table         : type=NOINIT
        .data.Mmu_tableArray_NS       : type=NOINIT
        .data.Mmu_tableArraySlot_NS   : type=NOINIT
        .data.Mmu_level1Table_NS      : type=NOINIT
    }

    ipc_data_buffer:       > C7X_1_DDR_SPACE
    .benchmark_buffer:     > C7X_1_DDR_SPACE ALIGN (32) 
    .l2mem              (NOLOAD)(NOINIT) : {} > L2SRAM
    .l1mem              (NOLOAD)(NOINIT) : {} > L1DSRAM
    .l3mem              (NOLOAD)(NOINIT) : {} > MSMCSRAM
    .resource_table: { __RESOURCE_TABLE = .;} > C7X_1_EXT_D
    .sensorData    : {} align(128)     > SHARED_DDR_SPACE
}

wtx loaded /lib/firmware/j784s4-c71_0-fw @ 0x0000000082000000: 10815944 bytes read in 477 ms (21.6 MiB/s)
Warning: Did not detect image signing certificate. Skipping authentication to prevent boot failure. This will fail on Security Enforcing(HS-SE) devices
"Error" handler, esr 0xbf000000
elr: 00000000808bed18 lr : 000000008086e388 (reloc)
elr: 00000000fff84d18 lr : 00000000fff34388
x0 : 0000000064e00000 x1 : 0000000000000000
x2 : 0000000000001800 x3 : 0000000000000140
x4 : 0000000000000000 x5 : 00000000000016c0
x6 : 0000000000000000 x7 : 0000000000e0c000
x8 : 0000000000000010 x9 : 0000000000000008
x10: 0000000000000008 x11: 00000000fde969e0
x12: 0000000000000000 x13: 0000000000000200
x14: 0000000000000004 x15: 0000000000000020
x16: 00000000fff2f854 x17: 0000000000000000
x18: 00000000fde85db0 x19: 0000000000000000
x20: 0000000082a4fbf0 x21: 0000000000000000
x22: 0000000082000000 x23: 00000000fde8a2c0
x24: 00000000fff8f3b8 x25: 0000000000000000
x26: 0000000064e00000 x27: 0000000000001800
x28: 0000000064e00000 x29: 00000000fde6f630

Code: d2800004 eb04005f 540000e1 d65f03c0 (f8236804)
Resetting CPU ...

resetting ...

It appears that our memory addresses are conflicting with the Linux boot process. After modifying the L1 and L2 addresses in the linker_c7x_freertos.cmd file as:

L2RAM_C7x_1 0x64E00000

L1RAM_C7_1 0xA8000000

 then Linux booting process work all fine. We got these wrong L1 and L2 addresses values from the FFTLIB's lnk.cmd (located at /ti-processor-sdk-09_02_00/ti-processor-sdk-rtos-j784s4-evm-09_02_00_05/fftlib_09_02_00_04/cmake/linkers/C7120/lnk.cmd). Our first question is why we have these L1 ans L2 addresses in the lnk.cmd.

Along with that, we have the following questions:

1. The lnk.cmd file located at /ti-processor-sdk-09_02_00/ti-processor-sdk-rtos-j784s4-evm-09_02_00_05/fftlib_09_02_00_04/cmake/linkers/C7120/lnk.cmd seems to have incorrect addresses for L1 and L2. What does these temporary placeholders for the L1SRAM in DDR mean in this file?

#if defined(FLAT_MEM)
-heap  0x7C00000
-stack 0x20000
--args 0x1000

--diag_suppress=10068 // "no matching section"
--cinit_compression=off

MEMORY
{
#if defined(RTL_TEST)
  L2SRAM (RWX)  : org = 0x64E00000, len = 0xB200000
  /* Temporary place holder for L1D*/
  L1DSRAM  (RWX): org = 0xA0000000, len = 0x004000
#else
  L2SRAM (RWX)  : org = 0x64E00000, len = 0xF800000
  /* Temporary place holder for L1D*/
  L1DSRAM  (RWX): org = 0xA0000000, len = 0x004000
#endif
  EXTMEM (RWX)  : org = 0x80000000, len = 0x800000
}

SECTIONS
{
  .sram_start START(_sram_start) > L2SRAM NOINIT

  .kernel: {
    *.obj (.text:optimized) { SIZE(_kernel_size) }
  } > L2SRAM

  .kernel_data SIZE(_data_size)

  .text:            > L2SRAM
  .text:touch:      > L2SRAM
  .neardata:        > L2SRAM
  .rodata:          > L2SRAM
  .bss:             > L2SRAM
  .init_array:      > L2SRAM
  .far:             > L2SRAM
  .fardata:         > L2SRAM
  .neardata         > L2SRAM
  .rodata           > L2SRAM
  .data:            > L2SRAM
  .switch:          > L2SRAM
  .stack:           > L2SRAM
  .args:            > L2SRAM align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:          > L2SRAM
  .cinit:           > L2SRAM
  .const:           > L2SRAM START(const_start) SIZE(const_size)
  .pinit:           > L2SRAM
  .cio:             > L2SRAM
  .stack:           > L2SRAM
  .staticData       > L2SRAM
  .msmcData         > L2SRAM
  .ddrData          > L2SRAM
  .l1dmemory        > L1DSRAM
  .l2dmemory        > L2SRAM
   xdc.meta:        > L2SRAM, type = COPY
}

#else // not FLAT_MEM

-heap  0x70000   // 448 kB
-stack 0x4000    //  16 kB
--cinit_compression=off
--args 0x1000
--diag_suppress=10068 // "no matching section"

MEMORY
{
#if SOC == j784s4
  MSMC3SRAM_CINIT (RWX)   : org = 0x70000000, len = 0x000100
  MSMC3SRAM (RWX)         : org = 0x70000100, len = 0x1fff00
  MSMC3SRAM_STATIC   (RWX): org = 0x70200000, len = 0x200000
  MSMC3SRAM_DATACN   (RWX): org = 0x70400000, len = 0x300000
  MSMC3SRAM_PT       (RWX): org = 0x70700000, len = 0x100000
  MSMCSRAM (RWX)          : org = 0x68000000, len = 0x300000
#else
  MSMCSRAM_CINIT (RWX)  : org = 0x70000000, len = 0x000100
  MSMCSRAM (RWX)        : org = 0x70000100, len = 0x3fff00
  EXTMEM_STATIC   (RWX): org = 0x80000000, len = 0x2000000
  EXTMEM_DATACN   (RWX): org = 0x82400000, len = 0x400000
  EXTMEM   (RWX): org = 0x82800000, len = 0x400000
  EXTMEMPAGE (RWX): org = 0x82C00000, len = 0x200000
#endif // SOC
  L2SRAM   (RWX): org = 0x64800000, len = 0x080000   // for J7
  L1DSRAM  (RWX): org = 0x64E00000, len = 0x004000   // 16kB, for J7


}

SECTIONS
{
  .sram_start START(_sram_start) > L2SRAM NOINIT

  .kernel: {
    *.obj (.text:optimized) { SIZE(_kernel_size) }
  } > L2SRAM

  .kernel_data SIZE(_data_size)
  .l1dmemory        > L1DSRAM
  .l2dmemory        > L2SRAM
#if SOC == j784s4
  .text:            > MSMC3SRAM
  .text:touch:      > MSMC3SRAM
  .text:_c_int00:   > MSMC3SRAM_CINIT
  .neardata:        > MSMC3SRAM
  .rodata:          > MSMC3SRAM
  .bss:             > MSMC3SRAM
  .init_array:      > MSMC3SRAM
  .far:             > MSMC3SRAM
  .fardata:         > MSMC3SRAM
  .neardata         > MSMC3SRAM
  .rodata           > MSMC3SRAM
  .data:            > MSMC3SRAM

  .data:pte:pte_lvl1_0000000000000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl0 > MSMC3SRAM_PT
  .data:pte:pte_lvl2_40000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl2_80000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64800000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64E00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D20000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D40000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D60000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64D80000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64DA0000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64DC0000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_64DE0000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70200000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70400000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_70600000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80200000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80400000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80600000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80800000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80A00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80C00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_80E00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81000000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81200000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81400000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81600000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81800000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81A00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81C00000 > MSMC3SRAM_PT
  .data:pte:pte_lvl3_81E00000 > MSMC3SRAM_PT

  .switch:          > MSMC3SRAM
  .stack:           > MSMC3SRAM
  .args:            > MSMC3SRAM align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:          > L2SRAM
  .cinit:           > MSMC3SRAM
  .const:           > MSMC3SRAM START(const_start) SIZE(const_size)
  .pinit:           > MSMC3SRAM
  .cio:             > MSMC3SRAM
  .stack:           > MSMC3SRAM
  .ddrData          > MSMC3SRAM_DATACN
  .staticData       > MSMC3SRAM_STATIC
  .msmcData         > MSMCSRAM
   xdc.meta:        > MSMC3SRAM, type = COPY
#else
  .text:            > MSMCSRAM
  .text:touch:      > MSMCSRAM
  .text:_c_int00:   > MSMCSRAM_CINIT
  .neardata:        > MSMCSRAM
  .rodata:          > MSMCSRAM
  .bss:             > MSMCSRAM
  .init_array:      > MSMCSRAM
  .far:             > MSMCSRAM
  .fardata:         > MSMCSRAM
  .neardata         > MSMCSRAM
  .rodata           > MSMCSRAM
  .data:            > MSMCSRAM
  .data:pte:pte_lvl1_0000000000000000 > EXTMEMPAGE
  .data:pte:pte_lvl0 > EXTMEMPAGE
  .data:pte:pte_lvl2_40000000 > EXTMEMPAGE
  .data:pte:pte_lvl2_80000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64800000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64E00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D20000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D40000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D60000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64D80000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64DA0000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64DC0000 > EXTMEMPAGE
  .data:pte:pte_lvl3_64DE0000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70200000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70400000 > EXTMEMPAGE
  .data:pte:pte_lvl3_70600000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80200000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80400000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80600000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80800000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80A00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80C00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_80E00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81000000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81200000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81400000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81600000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81800000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81A00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81C00000 > EXTMEMPAGE
  .data:pte:pte_lvl3_81E00000 > EXTMEMPAGE

  .switch:          > MSMCSRAM
  .stack:           > MSMCSRAM
  .args:            > MSMCSRAM align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:          > L2SRAM
  .cinit:           > MSMCSRAM
  .const:           > MSMCSRAM START(const_start) SIZE(const_size)
  .pinit:           > MSMCSRAM
  .cio:             > MSMCSRAM
  .stack:           > MSMCSRAM
  .ddrData          > EXTMEM_DATACN
  .staticData       > EXTMEM_STATIC
  .msmcData         > MSMCSRAM
   xdc.meta:        > MSMCSRAM, type = COPY
#endif

}
#endif

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j784s4/09_02_00_05/exports/docs/fftlib_09_02_00_04/docs/user_guide/build_instructions_linux.html

We believe that the discrepancy between the lnk.cmd file (where FFT .lib is created) and our linked file is causing the issue with the Linux boot process.

Attiya

Hi Attiya,

Thank you for providing more details about your application and what your motivation is - this helps us a lot to debug your issues further. 

First to clear up some of the questions regarding the linker file from FFTLIB:

The first section you see is ifdef for flat memory testing - this is for internal TI testing. For the addresses that map to the actual hardware, you should look starting at line 61 from the pasting of the linker file that you put in your previous post. There you will see on lines 86 and 87 the L2 and L1 addresses you expect. 

Attiya Mahmood said:

Also, .lib of FFTLIB assume what addresses of L1 and L2?

This would be based of the lines 86 and 87 that I mentioned earlier, and overall line 61 downward. 

Attiya Mahmood said:

The build instructions for FFTLIB mention that the test cases can be run in No Boot mode

The test case framework that comes with the library is designed to run baremetal, and it is recommended that the tests should be run this way. We have not done testing or added support for running the test cases in another way. 

Best,

Asha

Hi Asha,

Thank you for your detailed response; it's certainly helpful. We're now returning to our main question: what could be causing the Linux boot process to crash when we load our application onto the board? From what we've learned, it appears that something in the FFT LIB is conflicting with the boot process. When we run a very simple application (performing basic processing) using the correct L1 and L2 memory addresses, everything works fine. However, when we load our main application, which links FFTLIB, the system crashes. Could you help us understand what steps we can take, based on the linker memory file we shared earlier?

Also, is there any document by TI talks about L1 and L2 memories of C7 DSPs in detail and how are they integrated in the SOC with other memories. By default if they are configured as Cache or SRAM and how to change it?  Also, we did not find much detail of L1 and L2 in the TRM for J784s4.

Any suggestions would be greatly appreciated.

Thank you,

Attiya

Hi Attiya,

Attiya Mahmood said:

Thank you for your detailed response; it's certainly helpful. We're now returning to our main question: what could be causing the Linux boot process to crash when we load our application onto the board? From what we've learned, it appears that something in the FFT LIB is conflicting with the boot process. When we run a very simple application (performing basic processing) using the correct L1 and L2 memory addresses, everything works fine. However, when we load our main application, which links FFTLIB, the system crashes. Could you help us understand what steps we can take, based on the linker memory file we shared earlier?

Would you be able to provide the Linux boot logs of this? Want to see if this provides any more information for us to debug with. 

Attiya Mahmood said:

Also, is there any document by TI talks about L1 and L2 memories of C7 DSPs in detail and how are they integrated in the SOC with other memories. By default if they are configured as Cache or SRAM and how to change it?  Also, we did not find much detail of L1 and L2 in the TRM for J784s4.

I'll look internally regarding further documentation. In terms of cache settings and defaults and since you are working within a PDK-level environment, this is all done within PDK's CSL package. There is specific C7x APIs regarding the L1 and L2 cache settings.  

Best,

Asha

Hi Attiya,

More details regarding the L1 and L2 memories are in C71x DSP Corepac Technical Reference Manual (SPRUIQ3). We don't host this on ti.com, so I have reached out to your FAE to assist you in getting access if you do not already. 

Best,

Asha