Different Boot-times with D008K001 and D008K003 when booting from SPI-Flash

Stefan Fuchs

Other Parts Discussed in Thread: TMS320C6747

Hi All,

We're using a TMS320C6747 for an Audio-Application booting from SPI-Flash using the AIS-Bootloader. On our prototype-boards we used a TMX320C6747 (ROM-ID = D008K001). With this devices the StartUp-Time of our Application was approx 600ms (measured from the rising edge of the reset-signal). When changing toTMS320C6747 (with ROM-ID = D008K003) in the final release of the board the StartUp-Time increased to 1800 ms. To find the origin of this increasement in monitored the Clock of the SPI-Bootflash to see how long the Bootloader will need to read the Flash-Content.

Result:

With both ROM-Versions the behaviour is the same for the first 600ms (Flash-Content is read as stream). After this 600ms the bootloader stops reading and after a delay some additional words are read. With D008K001 this delay is just some ms, but with D008K003 this delay is 1200ms.

I tried to generate the AIS-File with "AISGen for D008K001" as well as with "AISGen for D008K003", but there was no change in behaviour.

Does anybody have any idea ?

Many thanx and best regards

Stefan

over 14 years ago

0 Daniel Allred over 14 years ago

TI__Genius 17355 points

Stefan,

Do you know what portion of the AIS file is loaded before you hit this delay. In other words, do you have any idea what AIS command the device is parsing/executing when this long delay takes place?

Obviously there were some code changes in the new ROM, but nothing that we are aware of that would explain the delay you are seeing?

Regards, Daniel

0 Stefan Fuchs over 14 years ago in reply to Daniel Allred

Prodigy 30 points

Hello Daniel,

Many thanx for fast response !

I monitored the SPI-Stream (@MISO) comming from the Bootflash and found the delay located
between end of "Section Load" (Addr = 0xC0000000, len = 0x0005A720) and "Validate CRC"
(See also extract of AIS-File generated with "aisparse.exe"). With the next step
i disabled the "Enable CRC"-Option. With disabled CRC the Delay disappeared, so i assume
the delay is caused by processing the CRC, still wondering why the processing-time is
different on D008K001 and D008K003.

Best regards
Stefan

Extract of AIS-File:
// ---------------------------------------------------------------
/* 0x00000000 */ 0x41504954, // MAGIC

/* 0x00000004 */ 0x58535963, // Sequential Read Enable

/* 0x00000008 */ 0x5853590D, // Function Execute
/* 0x0000000C */ 0x00030005, //   Function[5] PLL & Peripheral Clock Configuration
/* 0x00000010 */ 0x17010000, //   Arg[0]
/* 0x00000014 */ 0x000301C2, //   Arg[1]
/* 0x00000018 */ 0x0000000B, //   Arg[2]

/* 0x0000001C */ 0x58535907, // Write
/* 0x00000020 */ 0x00020004, //   Type
/* 0x00000024 */ 0x01C14188, //   Address (CFGCHIP3)
/* 0x00000028 */ 0x00000007, //   Data
/* 0x0000002C */ 0x00000000, //   Delay

/* 0x00000030 */ 0x5853590D, // Function Execute
/* 0x00000034 */ 0x00040002, //   Function[2] EMIFB SDRAM Configuration
/* 0x00000038 */ 0x00014420, //   Arg[0]
/* 0x0000003C */ 0x104921C8, //   Arg[1]
/* 0x00000040 */ 0x70080004, //   Arg[2]
/* 0x00000044 */ 0x0000081E, //   Arg[3]

/* 0x00000048 */ 0x58535903, // Enable CRC

/* 0x0000004C */ 0x58535901, // Section Load
/* 0x00000050 */ 0x00837000, //   Address (DSP L2 RAM, Local)
/* 0x00000054 */ 0x000002A0, //   Size
/* 0x00000058 */             //   Data
.
.
.
/* 0x000002F8 */ 0x58535902, // Validate CRC
/* 0x000002FC */ 0xEF6B5E3A, //   CRC
/* 0x00000300 */ 0xFFFFFD48, //   Seek

/* 0x00000304 */ 0x58535901, // Section Load
/* 0x00000308 */ 0xC0000000, //   Address (EMIFB SDRAM)
/* 0x0000030C */ 0x0005A720, //   Size
/* 0x00000310 */             //   Data
.
.
.   !!! DELAY = 1200ms !!!
.
.
/* 0x0005AA30 */ 0x58535902, // Validate CRC
/* 0x0005AA34 */ 0xEC3A54F2, //   CRC
/* 0x0005AA38 */ 0xFFFA58C8, //   Seek

/* 0x0005AA3C */ 0x58535901, // Section Load
/* 0x0005AA40 */ 0xC00AEDF0, //   Address (EMIFB SDRAM)
/* 0x0005AA44 */ 0x000074DC, //   Size
/* 0x0005AA48 */             //   Data
.
.
.
/* 0x00061F24 */ 0x58535902, // Validate CRC
/* 0x00061F28 */ 0xA2D46055, //   CRC
/* 0x00061F2C */ 0xFFFF8B0C, //   Seek

/* 0x00061F30 */ 0x58535901, // Section Load
/* 0x00061F34 */ 0xC00B62D0, //   Address (EMIFB SDRAM)
/* 0x00061F38 */ 0x00002A74, //   Size
/* 0x00061F3C */             //   Data
.
.
.
/* 0x000649B0 */ 0x58535902, // Validate CRC
/* 0x000649B4 */ 0x91EFCE4C, //   CRC
/* 0x000649B8 */ 0xFFFFD574, //   Seek

/* 0x000649BC */ 0x58535901, // Section Load
/* 0x000649C0 */ 0xC00B8D44, //   Address (EMIFB SDRAM)
/* 0x000649C4 */ 0x0000058C, //   Size
/* 0x000649C8 */             //   Data
.
.
.
/* 0x00064F54 */ 0x58535902, // Validate CRC
/* 0x00064F58 */ 0x2DA5C94E, //   CRC
/* 0x00064F5C */ 0xFFFFFA5C, //   Seek

/* 0x00064F60 */ 0x58535906, // Jump N Close
/* 0x00064F64 */ 0xC0059F00, //   Address (EMIFB SDRAM)

0 Daniel Allred over 14 years ago in reply to Stefan Fuchs

TI__Genius 17355 points

Stefan,

This information is helpful and we will investigate what the difference might be between the CRC calculations in the two ROM revisions. Just to be clear, do you see any measurable delays following other sections loads and CRC validations? Or is it just the first one?

Regards, Daniel

0 Stefan Fuchs over 14 years ago in reply to Daniel Allred

Prodigy 30 points

Hello Daniel,

Please find my measurement-results below (Target uses D008K003). As you can
see there is a delay after every section-load (length depending on size of
section).
Please note:
The delay formerly qualified with 1200ms is now stated with
1080ms since i used a different scope with better resolution for this measurement

Best regards
Stefan

// ---------------------------------------------------------------------

/* 0x0000004C */ 0x58535901, // Section Load
/* 0x00000050 */ 0x00837000, //   Address (DSP L2 RAM, Local)
/* 0x00000054 */ 0x000002A0, //   Size
/* 0x00000058 */             //   Data
.
.
. DELAY = 968us
.
.
/* 0x000002F8 */ 0x58535902, // Validate CRC
/* 0x000002FC */ 0xEF6B5E3A, //   CRC
/* 0x00000300 */ 0xFFFFFD48, //   Seek

/* 0x00000304 */ 0x58535901, // Section Load
/* 0x00000308 */ 0xC0000000, //   Address (EMIFB SDRAM)
/* 0x0000030C */ 0x0005A720, //   Size
/* 0x00000310 */             //   Data
.
.
. DELAY = 1080ms
.
.
/* 0x0005AA30 */ 0x58535902, // Validate CRC
/* 0x0005AA34 */ 0xEC3A54F2, //   CRC
/* 0x0005AA38 */ 0xFFFA58C8, //   Seek

/* 0x0005AA3C */ 0x58535901, // Section Load
/* 0x0005AA40 */ 0xC00AEDF0, //   Address (EMIFB SDRAM)
/* 0x0005AA44 */ 0x000074DC, //   Size
/* 0x0005AA48 */             //   Data
.
.
. DELAY = 87,2ms
.
.
/* 0x00061F24 */ 0x58535902, // Validate CRC
/* 0x00061F28 */ 0xA2D46055, //   CRC
/* 0x00061F2C */ 0xFFFF8B0C, //   Seek

/* 0x00061F30 */ 0x58535901, // Section Load
/* 0x00061F34 */ 0xC00B62D0, //   Address (EMIFB SDRAM)
/* 0x00061F38 */ 0x00002A74, //   Size
/* 0x00061F3C */             //   Data
.
.
. DELAY = 31,9 ms
.
.
/* 0x000649B0 */ 0x58535902, // Validate CRC
/* 0x000649B4 */ 0x91EFCE4C, //   CRC
/* 0x000649B8 */ 0xFFFFD574, //   Seek

/* 0x000649BC */ 0x58535901, // Section Load
/* 0x000649C0 */ 0xC00B8D44, //   Address (EMIFB SDRAM)
/* 0x000649C4 */ 0x0000058C, //   Size
/* 0x000649C8 */             //   Data
.
.
. DELAY = 4,17ms
.
.
/* 0x00064F54 */ 0x58535902, // Validate CRC
/* 0x00064F58 */ 0x2DA5C94E, //   CRC
/* 0x00064F5C */ 0xFFFFFA5C, //   Seek

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Different Boot-times with D008K001 and D008K003 when booting from SPI-Flash