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[FAQ] AM625 / AM623 / AM62A / AM62P / AM64x / AM243x Design Recommendations / Custom board hardware design – CAP_VDDSx CAP_VDDS

Kallikuppa Sreenivasa
Guru**** 155679 points
Part Number: AM625

Tool/software:

HI TI experts,

Could you provide recommendations on CAP_VDDSx, cap value and effect of the capacitor not mounted or shorted.

  • 0
    TI__Guru**** 155679 points

    HI Board designers, 

    Recommendations on CAP_VDDSx value 

    The LDO specification is 0.8uF to 1.5uF.  The capacitor should be within this range, considering bias, degradation over time etc.

     Q. With a 6.3V cap selected, considering the DC effect and other degradation, the cap value could go down to 0.7 uF.  Higher cap value may call for using a 0402 cap and that could have an effect on the layout.

    Does the capacitance depend on number of IOs used for the specific IO supply rail and the IOs current source/sink  or irrespective of the IO usage, the capacitance is required.

    https://www.kyocera-avx.com/docs/techinfo/CeramicCapacitors/mlcc-dc-bias-characteristics.pdf

    https://community.infineon.com/t5/Knowledge-Base-Articles/DC-Bias-characteristics-of-Multilayer-Ceramic-Capacitor-MLCC/ta-p/250035#.

    The cap value is independent of IO count and activity. It is required for stability of the LDO to generate BIAS supply. Any value beyond this specified range could make BIAS generator unstable resulting in over voltage stress.

    Additional Guidelines 

    Select cap with less the 1 ohm ESR
    Ensure the PCB loop inductance is < 2.5 nH
    Use smallest possible (0201 or greater) package to minimize loop inductance
    Refer SoC Data sheet

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 155679 points

    HI Board designers, 

     CAP_VDDSx voltage 

    It is not a fixed voltage. When the respective VDDSHV is operating at 1.8V, the pin should have the same potential as the VDDSHV source.

    When the respective VDDSHV is operating at 3.3V, it should have a potential that track to ½ of the VDDSHV source.

    When VDDSHV is ramping to 3.3V the LDO output will track VDDSHV until it gets up to about 2.4V. This is when bias supply circuit changes from what I call switch mode to LDO mode. At this point it begin to track ½ VDDSHV. I suspect the output capacitance will hold the 2.4V potential for a period of time before the IO bias circuits draw enough current to discharge the capacitor back down to the ½ VDDSHV potential.

    I would expect a similar thing to happen as the VDDSHV decays. When VDDSHV drops below 2.4V the bias supply circuit will switch back to switch mode, where the potential of VDDSHV is applied to the capacitor. 

    The CAP_VDDSn is optional when the IO group supply VDDSHVx is connected to 1.8V. When connected to 3.3V, the voltage to be considered for derating is the steady state DC output which is VDDSHVx/2. 

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 155679 points

    HI Board designers, 

    Effect of the CAP_VDDSx on the SOC performance

    The capacitor is connected to the output of an internal LDO.  The LDO will not function correctly if the capacitor is not connected to this pin or if this pin is shorted to ground.  The LDO powers circuits in each IO buffer associated with the respective bank of IOs.  The IO buffers will not operate as expected if the LDO is not operating as expected.  If the LDO is not operating properly the IO buffer circuits may be permanently damaged.   Any SOC that has been exposed to a condition that prevents the LDO from operating as expected should be removed, discarded, and replaced with a new unit.

    Regards,

    Sreenivasa