SK-AM62P-LP: AM62P package pin delay

Hello Jhon, 

Thank you for the query.

Can you clarify if you are looking for pin delay information for the AM62P package traces for DDR?

We currently support information related to pin delay- under NDA. 

Are you able to work with any of the TI sales team to get the files ?

Regards,

Sreenivasa

Hello Jhon, 

Refer below inputs i received from the DDR expert: 

Sreenivasa, the package pin delays can be found in the AM62P DDR layout guidelines , section 4

https://www.ti.com/lit/pdf/sprad66

Refer the below FAQ additionally 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1419150/faq-am625-am623-am625sip-am625-q1-am620-q1-am62a7-am62a3-am62p-am62p-q1-am6442-am2432-custom-board-hardware-design-s-parameter-and-ibis-model-of-io-buffer

Regards,

Sreenivasa

Hi,

Thank you for your reply.

Aside from DDR delays listed in the PDF file, there should be package delays for all other CPU High speed interface balls such as SD/MMC,DSI,LVDS,RGMII etc.

Typically there is a internal package delay file provided (as was the case for AM62x). These delays are required since they should be taken into account in length matching. There are no internal package delays included in the EVK reference .brd layout file.

Can you provide the delays for all other CPU balls?

Thank you,

Jhon

Hello Jhon

Thank you.

Let me check internally and update you.

Regards,

Sreenivasa

Hello Jhon,

Please refer below comments from the expert and provide your inputs.

we don’t supply that to customers.  Why do they need it?  I think for most peripheral frequencies, the package delay would be a small fraction of the rest of the board trace.  Is there a high speed peripheral they are concerned about?

Regards,

Sreenivasa