Tool/software:
I am new in the field of processor and its RAM memory. And I want to know if it es possible to connect the LPDDR4 SDRAM MT53E512M32D1 (Micron) to the Sitara AM64. It is a 16 Gbit RAM / 1 die / dual channel. Is possible the series-connection as proposed in https://www.jedec.org/sites/default/files/files/Marc_Greenberg_Mobile_and_IOT.pdf, page 9 ? I am unsettled because in the TRM AM64x/AM243x Technical Reference Manual (Rev. H, Chapter 8.1.1, there is following: DDRSSO supports memory bus features: up to 2 ranks and SDRAM address range up to 8 GByte and contrarily in chapter 8.1.1.1, there is: DDRSS0 does not support the following: only 1 rand designs are supported and only address range of up to 2 GBytes is supported. Can you resolve this contradiction.
The app-note AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) make following limitations (table 3-2): one channel, one rank, one die, one device. In this case the LPDDR4 SDRAM MT53E512M32D1 cannot be applied. Is this true?
Thank you for your help
Ricardo