Hi,
We have a DM816x/C6A816x/AM389x Evaluation Module of which we are using the PCIe interface to communicate with a configured Altera Cyclone IV FPGA development board.
During EVM Ubuntu boot, with FPGA card attached, the following PCIe information is given:
ti816x_pcie: Invoking PCI BIOS...
ti816x_pcie: Setting up Host Controller...
ti816x_pcie: Register base mapped @0xd0820000
ti816x_pcie: Starting PCI scan...
PCI: bus0: Fast back to back transfers disabled
PCI: bus1: Fast back to back transfers disabled
pci 0000:00:00.0: BAR 9: assigned [mem 0x20000000-0x21ffffff pref]
pci 0000:00:00.0: BAR 8: assigned [mem 0x22000000-0x220fffff]
pci 0000:01:00.0: BAR 0: assigned [mem 0x20000000-0x21ffffff 64bit pref]
pci 0000:01:00.0: BAR 0: set to [mem 0x20000000-0x21ffffff 64bit pref] (PCI address [0x20000000-0x21ffffff])
pci 0000:01:00.0: BAR 2: assigned [mem 0x22000000-0x2203ffff]
pci 0000:01:00.0: BAR 2: set to [mem 0x22000000-0x2203ffff] (PCI address [0x22000000-0x2203ffff])
pci 0000:01:00.0: BAR 3: assigned [mem 0x22040000-0x2207ffff]
pci 0000:01:00.0: BAR 3: set to [mem 0x22040000-0x2207ffff] (PCI address [0x22040000-0x2207ffff])
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0: bridge window [io disabled]
pci 0000:00:00.0: bridge window [mem 0x22000000-0x220fffff]
pci 0000:00:00.0: bridge window [mem 0x20000000-0x21ffffff pref]
PCI: enabling device 0000:00:00.0 (0140 -> 0143)
Note BAR0 is configured 64-bit prefetchable memory (32Mb) and BAR2 configured as 32-bit non-prefetchable memory (256Kb).
Our driver (originally supplied by Altera) then registers, reads the device configuration, scans and maps the bars. The following debugs are given during this stage:
probe(dev = 0xcc826c00, pciid = 0xbf1f87cc)
probe() ape = 0xcb754600
sizeof(struct ape_chdma_table) = 4096.
table_virt = ffc14000, table_bus = 0x 8a91a000.
PCI: enabling device 0000:01:00.0 (0140 -> 0142)
Enabled MSI interrupting.
Using a 64-bit DMA mask.
IRQ pin #1 (0=none, 1=INTA#...4=INTD#).
IRQ line #48.
Succesfully requested IRQ #112 with dev_id 0xcb754600
BAR0 0x20000000-0x21ffffff flags 0x0014220c
BAR2 0x22000000-0x2203ffff flags 0x00040200
BAR[0] mapped at 0xd56d8000 with length 16384(/33554432) flags = 0x0014220c.
BAR[2] mapped at 0xd5780000 with length 262144(/262144) flags = 0x00040200.
fpga_tests()
ptrHeader0 = 0xd56d8000
ptrHeader1 = 0x0
ptrHeader2 = 0xd5780000
We can then read/write BAR0 without any problems e.g.
printk(KERN_INFO "BAR 1 %d = %0llx ", i, ptrHeader0[i++]);
However, when it comes to accessing ANY part of BAR2 e.g.
printk(KERN_INFO "BAR 2 %d = %0llx ", i, ptrHeader2[i++]);
We get the following memory fault:
Unhandled fault: Precise External Abort on non-linefetch (0x1008) at 0xd5780000
Internal error: : 1008 [#1]
last sysfs file: /sys/module/pvrsrvkm/initstate
Modules linked in: altpciechdma(+) bufferclass_ti omaplfb pvrsrvkm TI81xx_hdmi ti81xxfb vpss syslink ipv6
CPU: 0 Not tainted (2.6.37 #1)
...
We have managed to determine via instrumentation, that BAR2 of the FPGA is never being accessed so assume the the problem is lying somewhere on the Linux side e.g. root complex.
Does anybody have some idea of what we may be doing wrong? We have looked and re-looked at this but can't find anything.
Many thanks,
Dave
