Tool/software:
Dear Team,
We are testing DRA821Ux CPU with Linux 09.02 sdk, we want to test audio using mcasp1 interface, by default in sdk there is no support added for mcasp1 controller.
Here are the changes we added to enable mcasp1 controller, kindly review the chnages, especially on clock configuration side
mcasp1: mcasp@2b10000 {
compatible = "ti,am33xx-mcasp-audio";
reg = <0x0 0x02b10000 0x0 0x2000>,
<0x0 0x02b18000 0x0 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
dma-names = "tx", "rx";
clocks = <&k3_clks 175 40>;
clock-names = "fck";
assigned-clocks = <&k3_clks 175 40>;
assigned-clock-parents = <&k3_clks 175 42>;
power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
Here we selected clocks based on output of k3conf tool
k3conf show clocks 175
|------------------------------------------------------------------------------|
| VERSION INFO |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024) |
| SoC | J7200 SR2.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0009 '9.2.4--v09.02.04 (Kool Koala))') |
|------------------------------------------------------------------------------|
|---------------------------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Clock Function |
|---------------------------------------------------------------------------------------------------------------------------------------------------------|
| 175 | 0 | DEV_MCASP1_MCASP_AHCLKX_POUT | Output clock |
| 175 | 2 | DEV_MCASP1_MCASP_AHCLKR_PIN | Input muxed clock |
| 175 | 3 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 4 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 5 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 6 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 11 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 12 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 13 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 14 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 175 | 19 | DEV_MCASP1_MCASP_ACLKR_PIN | Input clock |
| 175 | 21 | DEV_MCASP1_MCASP_AHCLKX_PIN | Input muxed clock |
| 175 | 22 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 23 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 24 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 25 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 30 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 31 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 32 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 33 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 175 | 38 | DEV_MCASP1_MCASP_AHCLKR_POUT | Output clock |
| 175 | 39 | DEV_MCASP1_MCASP_ACLKX_PIN | Input clock |
| 175 | 40 | DEV_MCASP1_AUX_CLK | Input muxed clock |
| 175 | 41 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 175 | 42 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 175 | 45 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 175 | 46 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 175 | 47 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 175 | 48 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 175 | 49 | DEV_MCASP1_VBUSP_CLK | Input clock |
| 175 | 50 | DEV_MCASP1_MCASP_ACLKR_POUT | Output clock |
| 175 | 51 | DEV_MCASP1_MCASP_ACLKX_POUT | Output clock |
|---------------------------------------------------------------------------------------------------------------------------------------------------------|
Regards,
Nikhil
