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AM6442: EP mode using FreeRTOS

Jonathan Navor
Genius 9475 points
Part Number: AM6442


Tool/software:

Hi Experts,

Customer wants to use AM6442 in EP mode using FreeRTOS and we don't want to use Linux. We need to use FreeRTOS due to low latency.

Could you please provide us with materials about enabling bus master bit using FreeRTOS and not Linux?

Thank you in advance.

Best regards,

Jonathan

  • 0
    TI__Mastermind 47836 points

    Hello Jonathan,

    Can you please elaborate more details about EP mode ?

    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    TI__Genius 9475 points

    Hi Anil,

    EP I mean PCIe EndPoint (EP) mode. 

    They have the AM6442 running FreeRTOS connected to my x86 PC running Windows 11 using male to male PCIe connector.
    The PC is operating as RC, the AM6442 as EP.
    They want the AM6442 to read a write any memory (not just driver assigned). For this, the BUS MASTER bit needs to be enabled in PCIe config space on the AM6442.
    The AM6442 is already seen by the x86 PC as valid PCIe EP thanks to example named "PCIE EP Enumeration" from MCU+ v10.

    My question is. When (in the init process) and how do I enable the bus master bit?

    Regards,

    Jonathan

  • 0 in reply to Jonathan Navor
    Mastermind 7540 points

    Hello Jonathan,

    From a PCIe perspective this bit is expected to be set by the firmware / OS / driver on the RC, not by the EP itself, if that's what you're asking. On the AM64x you could of course set it manually in the EP, see the pcie_msi_irq_ep example.

    I'd expect this bit to be set automatically by the Windows driver framework, when a driver starts DMA operations, but I haven't checked that explicitly. The KMDF examples from Microsoft don't use any code to explicitly set this bit.

    If your customer wants to manually set the BME bit, they could use the BUS_INTERFACE_STANDARD interface, similar to the code in triggerDwnStrIRQ() in the ti-sample-kmdf driver. Use GetBusData to read the COMMAND register, then use SetBusData to write back with BME set.

    That all said, I'm not sure if that would solve your customers real issue (whatever that really is). On the AM64x, the BME bit is not required to actually send outbound DMA transactions from the EP to the RC. Software "should" check this bit, but I don't think there's any hardware enforcing this. So basically the AM64x should already be able to send arbitrary DMA requests, even if the BME bit is not set.

    What exactly do you mean by

    Jonathan Navor said:
    They want the AM6442 to read a write any memory (not just driver assigned).

    A PCIe device is not expected to read/write arbitrary memory, and I'd expect this to conflict with security measures built into operating systems. An IOMMU for example would catch any access to memory that wasn't specifically assigned to this device. Not sure if / how extensively Windows 11 uses this feature.

    Regards,

    Dominic