AM69: Disabling caches before or in U-Boot

Hello Daisuke-san,

arch/arm/mach-k3/j784s4_init.c

spl_enable_dcache

That can be commented out. That said I am not sure where kernel turns of the cache.

Daisuke Maeda said:

They want to test LPDDR4 after disabling the caches.

Not sure what is the point of this but might not be so trivial to disable A72 cahces.

- Keerthy

Hi Keerthy-san,

Thank you for your reply.

If "spl_enable_dcache" is commented out, are L1D and L2 caches for A72 disabled, or L1D cache for R5F?

Is "j784s4_init.c" a source code for the Linux kernel?

Our customer wants to know how to disable caches for A72 and R5F before or in U-Boot.

In the case of L3 cache, the cache configuration is done in R5 bootloader and can be changed by following the steps below:

software-dl.ti.com/.../How_to_Configure_MSMC_memory.html

Best regards,

Daisuke

Hi Keerthy-san,

Thank you for your reply.

Can the latest SDK (10.00.07.06) also disable the cache in the same way?

"spi_enable_cash()" is used in k3_mem_init() in j784s4_init.c. "spl_enable_dcache" cannot be found.

To disable the A72 & R5 caches, is "spi_enable_cash()" commented out?

The functions related to cache operations for A72 (v8-A) can be found in the following source file:

arch/arm/cpu/armv8/cache_v8.c
dcache_enable()
dcache_disable()
icache_enable()
icache_disable()

In which source files are the functions related to cache operations for R5 (v7-R)?

Are the cache operations for R5 really done in U-Boot?

Best regards,

Daisuke

Hello Daisuke-san,

There should be something under arch/arm. 

But Linux runs on armv8. So for Linux it should not matter.

Best regards,

Keerthy 

Hi Keerthy-san,

Thank you for your reply.

U-Boot runs on A72, so the cache can be configured for A72, but not for R5, right?

Does R5 SPL (tiboot3.bin) need to be modified to configure cache for R5?

If so, which functions or source codes do the cache operations in R5 SPL?

Best regards,

Daisuke

Hello Daisuke-san,

What do you want to try on R5? A72 will boot Linux. I want to understand what you want to try on R5 without cache?

Best regards,

Keerthy 

Hi Keerthy-san,

Thank you for your reply.

Our customer wants to test LPDDR4 after disabling the caches on the A72 and R5 respectively.

Best regards,

Daisuke

Hi,

I have shared from the U-Boot / SPL side. 

dcache_enable()
dcache_disable()
icache_enable()
icache_disable()

I am not sure on the Linux side. They can test for A72 on the U-Boot without caches.

- Keerthy

Hi Keerthy-san,

Thank you for your reply.

We have already found the functions related to cache operations for A72 in the U-Boot source file.

Daisuke Maeda said:

The functions related to cache operations for A72 (v8-A) can be found in the following source file:

arch/arm/cpu/armv8/cache_v8.c
dcache_enable()
dcache_disable()
icache_enable()
icache_disable()

Could you please tell me how to disable cache for R5?

Does R5 SPL (tiboot3.bin) need to be modified to disable cache for R5?

If so, which functions or source codes do the cache operations in R5 SPL?

Best regards,

Daisuke

Hi Keerthy-san,

Thank you for your reply.

"armv7m" supports the Cortex-M architecture, but will not support R5F.

"armv7" directory will be referenced for R5F.

git.ti.com/.../armv7

The following functions seem to be usable to disable the caches in U-Boot.

dcache_disable()
icache_disable()

Can the functions also be used in R5 SPL?

If so, which are the source codes for R5 SPL?

Best regards,

Daisuke

Daisuke Maeda said:

If so, which are the source codes for R5 SPL?

This is a transient phase. Those calls can be used but how do they plan to test DDR from R5 SPL?
Are they adding code in R5 SPL to test DDR?

- Keerthy

Hi Keerthy-san,

Thank you for your reply.

Our customer has not found the source codes for R5 SPL. They want to know which source codes are for R5 SPL.

Best regards,

Daisuke