• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 100 subscribers
  • Views 739 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] AM625: PCB Pattern Recommendations for Specific Peripherals

Mari Tsunoda
Expert 5726 points

Part Number: AM625

Tool/software:

Hi Team,

My customer is creating their PCB and have a few questions.

Is there any recommendations or recommended values (for interconnect length or CLK-to-DATA interconnect difference) for the peripherals below? Is there any documentation that lists this?

①　eMMC、SD card
②　LVDS
③　SPI、QSPI（OSPI）

Best regards,

Mari Tsunoda

  • 0
    TI__Guru 64045 points

    Yes, these requirements are defined in the respective Timing Conditions table found in the timing sections of the datasheet.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Mastermind 30392 points

    The max route length Is a common question raised by customer form time to time:

    a uniform detail answer would help. 

    For AM62x  LVDS/OLDI interface, how to interpret the length from the parameter in datasheet. 

    Actually did not find timing data in datasheet.

  • 0 in reply to Tony Tang
    TI__Guru 64045 points

    Trace length requirements are considered for peripherals that have a specific requirement. For example, we define PCB trace delays for the eMMC and SD Card peripherals because PCB trace delays had to be included in our timing closure of AM62x for it to meet the requirements defined in the respective industry standard.

    In some cases, we do not have an industry standard.

    For some of these cases, a peripheral is timing closed based on a compilation of timing data from a set of devices which are likely to be connected to the peripheral. This collection of timing data is used in lieu of an industry standard and PCB trace delay expectations are included in our timing closure of AM62x. 

    There are also cases where we do not have enough timing data for attached devices to consider the impact of PCB delays. OLDI is an example of this case, where we do not know how much variability a specific display panel allows between the arrival of clock and data signals. Therefore, we only define our timing variability between the source synchronous output signals. The customer must research the requirements of their specific display panel to determine how much margin remains for PCB trace length matching.

    Regards,
    Paul