McASP on OMAP-L138

Boris Ruvinsky said:

1.  According to the User Guide (SPRUH77) - McASP internal reference CLK can be AUXCLK only (which is the input oscillator clock) - page145. Is this correct?

 No sure what internal reference clock is referring to here. There are multiple clocks, AHCLKX/R, ACLKX/R, and FSX/R. AHCLKX/R can be derived internally (via AUXCLK) or externally via another clock source. The same is true with ACLKX/R and FSX/R

Boris Ruvinsky said:

2.  At the same tine - the Module CLK for MsASP is SYSCLK2 = 1/2CPU CLK. Can this SYSCLK2 be used as reference for serial clock ACLKR/X generation?

Yes

Boris Ruvinsky said:

2.  The external reference (for ACLKR/X) CLK (up to 40MHz) can be connected to AHCLKX/R as external source only. Is this correct?

No. ACLKX/R is either derived internally or externally. Please refer to Figure 25-15 in the Technical Reference Manual (TRM)

Boris Ruvinsky said:

3.  The timing parameters in DS  SMOMAPL138 (SLVSAQ9) - Table 5-54 on page153 - the parameters 5, 6, 7, 8 - are timed to ACLKR/X but the timing is is different depending of AHCLKR/X Internal/external - not ACLKR/X. Is this Table 5-54 correct? On McBSP the timing DR to CLKR has a variation  depending of CLKR/X internal/external. Should it be the same for McASP? It sounds more logical to me.

Table 5-54 is correct. McBSP is different that McASP.

Boris Ruvinsky said:

4.  The CLK polarity for ACLKX and ACKR can be different if ASYNC = '1'. Is this correct? 

ASYNC means that you can run the clocks in an asynchronous fashion with respect to timing, however does not control clock polarity.Clock polarity is dependent on the polarity bit setting. Please refer to Figure 25-16 in the TRM for details.

Boris Ruvinsky said:

5.  If the above correct - the AFSX can be driven out by CLKX falling edge CLKXP ='1' and receive in by CLKR falling edge CLKRP = '0'. Is this correct?

This bit controls controls if data is shifted out on the rising or falling edge on AXR[X]. AFSX/R polarity is defined by another source. Refer to Figure 25-17 in the TRM for details.

Hello Drew.

Thank you for your repond and help.

I just copied here your respond to ask some questions:

Boris Ruvinsky said:

1.  According to the User Guide (SPRUH77) - McASP internal reference CLK can be AUXCLK only (which is the input oscillator clock) - page145. Is this correct?

 No sure what internal reference clock is referring to here. There are multiple clocks, AHCLKX/R, ACLKX/R, and FSX/R. AHCLKX/R can be derived internally (via AUXCLK) or externally via another clock source. The same is true with ACLKX/R and FSX/R

Boris Ruvinsky said:

2.  At the same tine - the Module CLK for MsASP is SYSCLK2 = 1/2CPU CLK. Can this SYSCLK2 be used as reference for serial clock ACLKR/X generation?

Yes

You answered YES here. That means SYSCLK2 can be used to generate ACLKR/X. Is this correct?

I could not find this in UM (SPRUH77).

On page145 "McASP Clocking Diagram" - I can see that Clock Generator" is connected to PLL0_AUXCLK and external clocks.

On page1060-1061 - "Transmit Clock" and "received Clock" - "(HCLKX) from McASP internal clock source AUXCLK".

Based on that - the internal clock source for McASP is AUXCLK which is the same as OSCIN. Is this correct?

Boris Ruvinsky said:

2.  The external reference (for ACLKR/X) CLK (up to 40MHz) can be connected to AHCLKX/R as external source only. Is this correct?

No. ACLKX/R is either derived internally or externally. Please refer to Figure 25-15 in the Technical Reference Manual (TRM)

Boris Ruvinsky said:

3.  The timing parameters in DS  SMOMAPL138 (SLVSAQ9) - Table 5-54 on page153 - the parameters 5, 6, 7, 8 - are timed to ACLKR/X but the timing is is different depending of AHCLKR/X Internal/external - not ACLKR/X. Is this Table 5-54 correct? On McBSP the timing DR to CLKR has a variation  depending of CLKR/X internal/external. Should it be the same for McASP? It sounds more logical to me.

Table 5-54 is correct. McBSP is different that McASP.

Boris Ruvinsky said:

4.  The CLK polarity for ACLKX and ACKR can be different if ASYNC = '1'. Is this correct? 

ASYNC means that you can run the clocks in an asynchronous fashion with respect to timing, however does not control clock polarity.Clock polarity is dependent on the polarity bit setting. Please refer to Figure 25-16 in the TRM for details.

Boris Ruvinsky said:

5.  If the above correct - the AFSX can be driven out by CLKX falling edge CLKXP ='1' and receive in by CLKR falling edge CLKRP = '0'. Is this correct?

This bit controls controls if data is shifted out on the rising or falling edge on AXR[X]. AFSX/R polarity is defined by another source. Refer to Figure 25-17 in the TRM for details.

 Thank you for your help,

Boris Ruvinsky

Boris Ruvinsky said:

You answered YES here. That means SYSCLK2 can be used to generate ACLKR/X. Is this correct?

I could not find this in UM (SPRUH77).

On page145 "McASP Clocking Diagram" - I can see that Clock Generator" is connected to PLL0_AUXCLK and external clocks.

On page1060-1061 - "Transmit Clock" and "received Clock" - "(HCLKX) from McASP internal clock source AUXCLK".

Based on that - the internal clock source for McASP is AUXCLK which is the same as OSCIN. Is this correct?

Sorry, I didn't read your question clearly. SYSCLK2 clocks the Module (Internal Logic, State Machines, etc). If you want to derive ACLKX/R internally, then this needs to be a divide down value from AHCLKX/R. The internal clock source for AHCLKS/R is AUXCLK, else it can additionally be supplied externally This is shown in Sections 25.2.2.1 and 25.2.2.2 in SPRU77

AUXCLK is the output of the Main System Oscillator. Refer to Section 8.2 for details of the clock tree for the device.

Hello Drew.

Thank you for your help.

I have one more question about McASP.

1.  When Transmit Frame Sync released from reset (XFRST bit in GBLCTL register set to '1' the Frame Sync (AFSX) starts generating as programmed. Is it correct?

2.  Will AFSX start immediately as active output and then switch according to the programmed cycle?

3.  Or the first active AFSX will appear on the McASP output after the number of Serial clocks (AFSX period which can be 256 clocks for example)

4.  Is there any deterministic delay from XFRST =1 to the first AFSX active on the output?

Thank you again for your help,

Boris Ruvinsky