Other Parts Discussed in Thread: SK-AM64B, , CDCLVC1310
Tool/software:
Hi,
In AM6422 evaluation board SK-AM64B. It connect the EXT_REFCLK1 to CLKOUT0 signal. i have some question about it.
1. EXT_REFCLK1 is 3.3V. Why it connect to a 1.8V clock buffer. Will it damage the buffer?
2. If EXT_REFCLK1 output the signal to 1.8V buffer. How the clock generate from EXT_REFCLK1. looks like the buffer also support the main domain clock input. if the main domain doesn't has the input clock firstly, how the EXT_REFCLK1 generate clock signal. if I am wrong, how the circuit work?
the PROC101D evaluation board has similar questions. looks like logic level is not same. And if the buffer CDCLVC1310 input is select to primary. how the main/mcu domain clock work firstly.
Best Regards,
Shu