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TDA4AH-Q1: SERDES2 SGMII configuration

Part Number: TDA4AH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi,

  Platform:TDA4VH J784s4-evm(Our company test board cards)

  SDK:ti-processor-sdk-linux-adas-j784s4-evm-09_01_00_06

  We added the following patches.

   In order to enable SGMII mode on J784S4, please ensure that the following commits are present in your Linux Source:
1. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/drivers/phy/ti/phy-gmii-sel.c?h=ti-linux-6.6.y&id=b64dce7e8b3032252df43667d46cf37b28c6b943
2. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/drivers/phy/ti/phy-j721e-wiz.c?h=ti-linux-6.6.y&id=888fe8dd74a2dc3e32396b8cd9e4b76069db87eb
3. https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/drivers/net/ethernet/ti?h=ti-linux-6.6.y&id=e63dcf67e8c90d8e0f26728de7fe96cc3dda57da

    We want to use all four lanes of serdes2  and configure as sgmii at once(&serdes2 create four serdes_sgmii_xx_link{}). However, after the configuration, none of them can work properly

    We tried to configure it separately(&serdes2 creates only one serdes_sgmii_xx_link). Then start the board to test the corresponding network port

     serdes2 lane2 -> qsgmii line1 , the network can be used normally. 

     serdes2 lane3 -> qsgmii line2,the network can be used normally.

     serdes2 lane0 -> qsgmii line5,the network can not be used.

     serdes2 lane1 -> qsgmii line6,the network can not be used.

     The k3-j784s-evm-quad-eth-exp1.dtso :

      

&main_cpsw0_port1 {
status = "okay";
phy-handle = <&cpsw9g_phy1>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_sgmii_3_link>;
phy-names = "mac", "serdes";
};

&main_cpsw0_port2 {
status = "okay";
phy-handle = <&cpsw9g_phy2>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_sgmii_4_link>;
phy-names = "mac", "serdes";
};

&main_cpsw0_port3 {
status = "okay";
phy-handle = <&cpsw9g_phy3>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_1_link>;
phy-names = "mac", "serdes";
};

&main_cpsw0_port4 {
status = "okay";
phy-handle = <&cpsw9g_phy4>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_2_link>;
phy-names = "mac", "serdes";
};

&main_cpsw0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;
	bus_freq = <1000000>;
	#address-cells = <1>;
	#size-cells = <0>;

    // sgmii1 -- J784S4_SERDES2_LANE2_QSGMII_LANE1 -- addr:1
	cpsw9g_phy1: ethernet-phy@1 {
		reg = <1>;
	};
	
	// sgmii2 -- J784S4_SERDES2_LANE3_QSGMII_LANE2 -- addr:2
	cpsw9g_phy2: ethernet-phy@2 {
		reg = <2>;
	};
	
	// sgmii5 -- J784S4_SERDES2_LANE0_QSGMII_LANE5 -- addr:16
	cpsw9g_phy2: ethernet-phy@16 {
		reg = <16>;
	};
	
	// sgmii6 -- J784S4_SERDES2_LANE1_QSGMII_LANE6 -- addr:19
	cpsw9g_phy2: ethernet-phy@19 {
		reg = <19>;
	};
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
		      <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
};

&serdes_wiz2 {
	status = "okay";
};

&serdes2 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes2_sgmii_1_link: phy@1 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 1>;
	};
	
	serdes2_sgmii_2_link: phy@2 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 2>;
	};
	
	serdes2_sgmii_3_link: phy@3 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 3>;
	};
	
	serdes2_sgmii_4_link: phy@4 {
		reg = <3>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 4>;
	};
};

    1、 When lane channels are configured separately, why do two lanes work and the other two not? What might be the cause of this.

     2、When four lanes are configured at the same time, none of them work properly. And the ehternet phy probe function is called repeatedly when the kernel starts. What might be the cause of this.

Thanks,

  • Hi

        1、 When lane channels are configured separately, why do two lanes work and the other two not? What might be the cause of this.

         2、When four lanes are configured at the same time, none of them work properly. And the ehternet phy probe function is called repeatedly when the kernel starts. What might be the cause of this.

    1 is not the correct way to do this, you should configure the 4 lanes simultaneously.

    Are you using SBL or SPL boot mode?

    Can you share your modifications in device-tree for configuring four lanes simultaneously.

    Regards,
    Tanmay

  • Hi,

    1、Do you mean to configure 4 lanes in a &serdes2_sgmii_1_link? Yes, I do. But only two lanes work. Lane2 and  lane3 can work. Lane0 and lane1 can not.What might have caused the other two lanes to be blocked.

    The  k3-j784s-evm-quad-eth-exp1.dtso :

    &main_cpsw0_port1 {
    status = "okay";
    phy-handle = <&cpsw9g_phy1>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_port2 {
    status = "okay";
    phy-handle = <&cpsw9g_phy2>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_port3 {
    status = "okay";
    phy-handle = <&cpsw9g_phy3>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_port4 {
    status = "okay";
    phy-handle = <&cpsw9g_phy4>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_mdio {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&mdio0_pins_default>;
    	bus_freq = <1000000>;
    	#address-cells = <1>;
    	#size-cells = <0>;
    
        // sgmii1 -- J784S4_SERDES2_LANE2_QSGMII_LANE1 -- addr:1
    	cpsw9g_phy1: ethernet-phy@1 {
    		reg = <1>;
    	};
    	
    	// sgmii2 -- J784S4_SERDES2_LANE3_QSGMII_LANE2 -- addr:2
    	cpsw9g_phy2: ethernet-phy@2 {
    		reg = <2>;
    	};
    	
    	// sgmii5 -- J784S4_SERDES2_LANE0_QSGMII_LANE5 -- addr:16
    	cpsw9g_phy2: ethernet-phy@16 {
    		reg = <16>;
    	};
    	
    	// sgmii6 -- J784S4_SERDES2_LANE1_QSGMII_LANE6 -- addr:19
    	cpsw9g_phy2: ethernet-phy@19 {
    		reg = <19>;
    	};
    };
    
    &serdes_ln_ctrl {
    	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
    		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
    		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
    		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
    		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
    		      <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
    };
    
    &serdes_wiz2 {
    	status = "okay";
    };
    
    &serdes2 {
    	status = "okay";
    	#address-cells = <1>;
    	#size-cells = <0>;
    
    	serdes2_sgmii_1_link: phy@1 {
    		reg = <0>;
    		cdns,num-lanes = <4>;
    		#phy-cells = <0>;
    		cdns,phy-type = <PHY_TYPE_SGMII>;
    		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>, <&serdes_wiz2 3>, <&serdes_wiz2 4>;
    	};
    
    };

    The following is the value of the registers for serdes2:

    devmem2 0x05020404
    Read at address  0x05020404 (0xffffa2c62404): 0x00000000
    
    devmem2 0x05020408
    Read at address  0x05020408 (0xffffabef4408): 0x18100000
    
    devmem2 0x0502040C
    Read at address  0x0502040C (0xffffbb1d340c): 0xA2800000
    
    devmem2 0x05020480
    Read at address  0x05020480 (0xffff905c2480): 0x70800000
    
    devmem2 0x05020484
    Read at address  0x05020484 (0xffffab146484): 0x00010002
    
    devmem2 0x05020488
    Read at address  0x05020488 (0xffff9c348488): 0x00000104
    
    devmem2 0x0502048C
    Read at address  0x0502048C (0xffff9afe348c): 0x00000002
    
    devmem2 0x050204C0
    Read at address  0x050204C0 (0xffff86b8a4c0): 0x70800000
    
    devmem2 0x050204C4
    Read at address  0x050204C4 (0xffffbf2404c4): 0x00010002
    
    devmem2 0x050204C8
    Read at address  0x050204C8 (0xffff90ed04c8): 0x00000106
    
    devmem2 0x050204CC
    Read at address  0x050204CC (0xffff85a114cc): 0x00000002
    
    devmem2 0x05020500
    Read at address  0x05020500 (0xffff889a5500): 0x70800000
    
    devmem2 0x05020504
    Read at address  0x05020504 (0xffff9cd55504): 0x00010002
    
    devmem2 0x05020508
    Read at address  0x05020508 (0xffffaba61508): 0x00000105
    
    devmem2 0x0502050C
    Read at address  0x0502050C (0xffff8f1c750c): 0x00000012
    
    devmem2 0x05020540
    Read at address  0x05020540 (0xffffb1b09540): 0x70800000
    
    devmem2 0x05020544
    Read at address  0x05020544 (0xffff8343b544): 0x00010002
    
    devmem2 0x05020548
    Read at address  0x05020548 (0xffff88eb9548): 0x00000103
    
    devmem2 0x0502054c
    Read at address  0x0502054C (0xffff9791554c): 0x00000012
    
    devmem2 0x05020E000
    Read at address  0x0502E000 (0xffffafbb1000): 0x00490011

    2、We use SPL boot mode.

    3、If I put serdes2 lane2 -> sgmii 7, this channel won't work either. (This channel will work only if serdes2 lane2 -> sgmii 1)

          If I put serdes2 lane3 -> sgmii 8, this channel won't work either. (This channel will work only if serdes2 lane3 -> sgmii 2)

          The reference manual shows that serdes2 lane2 can be configured as sgmii 1 or sgmii 7, and serdes2 lane3 can be configured as sgmii 2 or      sgmii 8. What might be causing this.

    Thanks,

  • Hello,

    If you plan to use SGMII7 and SGMII8, then MAC Port 7 and MAC Port 8 should be enabled and MAC Port 1 and MAC Port 2 should be disabled in the device-tree. Currently, MAC Port 1 and MAC Port 2 have been enabled:

    &main_cpsw0_port1 {
    status = "okay";
    phy-handle = <&cpsw9g_phy1>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_port2 {
    status = "okay";
    phy-handle = <&cpsw9g_phy2>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };

    The above change should be removed.
    The following change should be made instead:
    &main_cpsw0_port7 {
    status = "okay";
    phy-handle = <&cpsw9g_phy1>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_port8 {
    status = "okay";
    phy-handle = <&cpsw9g_phy2>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };

    It is being assumed that CPSW9G_PHY1 and CPSW9G_PHY2 are connected to SGMII 7 (MAC Port 7) and SGMII 8 (MAC Port 8). If they aren't, that needs to be fixed.

    Regards,
    Siddharth.

  • Hello

      I want to get to my first question. Why can serdes2 lane0 and lane1 not be connected properly

    Thanks

  • I want to get to my first question. Why can serdes2 lane0 and lane1 not be connected properly

    If LANE0 and LANE1 are being connected to SGMII5 and SGMII6, the following changes in your device-tree are incorrect since they are still referring to SGMII3 and SGMII4:

    &main_cpsw0_port3 {
    status = "okay";
    phy-handle = <&cpsw9g_phy3>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };
    
    &main_cpsw0_port4 {
    status = "okay";
    phy-handle = <&cpsw9g_phy4>;
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_1_link>;
    phy-names = "mac", "serdes";
    };

    Replace main_cpsw0_port3 with main_cpsw0_port5 and replace main_cpsw0_port4 with main_cpsw0_port6.

    SGMIIx => main_cpsw0_portx

    Regards,
    Siddharth.