DM365 VPFE: PCLK question

Chris Meng

Hi,

Would you pls help to confirm if below understanding is correct?

If VPSS_CLK_CTRL.PCLK_INV =0, the ISIF captures on the rising of edge of the PCLK signal.

If VPSS_CLK_CTRL.PCLK_INV =1, the ISIF captures on the falling edge of the PCLK signal.

0 Manjunath Hadli56783 over 13 years ago

I think it is correct. Although the datasheet does not make it crsytal clear, in a page it says:

"PCLK can be inverted for negative edge support, selectable by the PCLK_INV bit of VPSS_CLK_CTRL

So , negetive edge = falling edge is what I would think.

Thx,

-Manju

0 ZHIQING WANG over 13 years ago in reply to Manjunath Hadli56783

hi,Manju

Would you tell me the literature number who says things about PCLK's edge setting?I was about to double check that point.

0 Manjunath Hadli56783 over 13 years ago in reply to ZHIQING WANG

page 60.

The VPBE clock control is in the System module in the VPSS_CLK_CTRL register. The various modes

shown in Figure 34 are described here.

• VPSS_MUXSEL = 0 or 1: Both the VENC and DAC get their clock from one of the following three

sources: PLLC1SYSCLK6 clock, PLLC2SYSCLK5 clock, or MXI crystal input.

• VPSS_MUXSEL = 2: EXTCLK mode - Both the DAC and VENC receive the external input clock via

the EXTCLK port.

• VPSS_MUXSEL = 3: PCLK mode - Both the DAC and VENC receive the PCLK. When PCLK

frequency is 27 MHz or 74.25 MHz, the DAC clock can be enabled to get SDTV, HDTV video output.

PCLK can be inverted for negative edge support, selectable by the PCLK_INV bit of VPSS_CLK_CTRL

register

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