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PROCESSOR-SDK-J784S4: TI devnp_cpsw9g.so driver diagnostics

Mayank Sharma
Prodigy 240 points
Part Number: PROCESSOR-SDK-J784S4

Tool/software:

Dear TI support,

I want details on supported run time diagnostics and troubleshooting options of

  • devnp_cpsw9g.so
  • Enet LLD
  • UDMA LLD

Diagnostics parameters:

  • Packet statistics
    • Packet loss due to buffer overflow
    • Packet loss due to other reasons
    • TX Ring buffer status
    • RX Ring buffer status
  • Driver crash dumps
  • Tx/Rx maximum buffer (UDMA) utilization during runtime. 

  • 0
    TI__Guru 65160 points

    Hi,

    S/W side there will not be any loss, If H/W buffer is full packets will not be submitted to Hardware for Tx path.
    Also, in case of Rx If H/W buffer is not empty packets will be dropped at H/W side, can be found from CPSW Statistics.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 240 points

    Hi Sudheer,

    On the RX side, if the packet is dropped due to not having space in the buffer, I believe this is noticed within the ring buffer and UDMA. 

    Is there a way to know/diagnose

    1. if the UDMA buffer is full/overflow? 
    2. Is there a way to know the maximum Rx UDMA ring buffer consumed at run time?

    Regards,

    Mayank

  • +1 in reply to Mayank Sharma
    TI__Guru 65160 points

    Hi,

    Mayank Sharma said:

    On the RX side, if the packet is dropped due to not having space in the buffer, I believe this is noticed within the ring buffer and UDMA. 

    Is there a way to know/diagnose

    Before UDMA, There is CPSW Host Port present, External Port receiving data will be copied to Host Port Tx FIFO.
    If Host Port Tx FIFO is full the external port receive data will be dropped to accept further incoming data which will be identify from Top of FIFO Drop at external Port statistics.

    Note above explanation is for receiving data intended to reach Host Port and SoC core for processing.

    In above case UDMA or Ring buffer doen't know about anything. It can receive the data when free descriptors are submitted to flows, If not descriptors are submitted then no data movent to rings from CPSW Host Port.

    Mayank Sharma said:
    Is there a way to know the maximum Rx UDMA ring buffer consumed at run time?

    I think Ring will move in forward direction till the Length and then start again from base address. So, all ring buffers will be used for transfer.

    Best Regards,
    Sudheer