TDA4VM-Q1: Jacinto7_DDRSS_RegConfig DRAM Timing Mapping problems For Micron MT53E1G32D2FW-046

Tool/software:

Hi, Dear Expert.

We use Jacinto7_DDRSS_RegConfig tool with default setting for TDA4VM, and face some DRAM Timing Mapping problems.

1. Read output timing not match.

Should we modify DQS Max output timing to 3.5ns?

2.Core Timing not match.

Should we modify tRCD to 18ns?

Should we modify tRpb to 18ns/3nCK?

Should we modify tRpab to 21ns/3nCK?

Should we modify tRRD TO 4nCK/10ns?

Many Thanks

Gibbs