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C667x CLKOUT for 8 DDR3 devices

Nori Shinozaki
Intellectual 2430 points

Hello,

There are two DDR3CLKOUT ports in C667x.

From "DDR3 Design Requirements for KeyStone Devices", is this a correct connection for  total 8 8 bit DDR3 devices?

DDR3CLKOUT0 - DDR3 - DDR3 - DDR3 - DDR3

DDR3CLKOUT1 - DDR3 - DDR3 - DDR3 - DDR3

Best Regards,

Nori Shinozaki

  • 0
    TI__Mastermind 42545 points

    DDR3CLKOUT1 should only be used if a second rank of memory is part of the design.  If you have a single rank of memory 64bits wide using eight x8bit devices they should all be connected to DDR3CLKOUT0 with the same fly-by routing as the address and control signals.  DDR3CLKOUT1 and DDRCE1z should be left unconnected. 

  • 0 in reply to Bill Taboada
    TI__Intellectual 2430 points

    Hello,

    Thanks,

    So for eight x8bit DDRs, we should use,

    # For Second Ranked:

    DDR3CLKOUT1 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3

    # For Single Ranked:

    DDR3CLKOUT0 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3 - DDR3

    Is this correct daisy chaining?

    May I ask why these two port should be chosen like this?

    Regards,

    Nori Shinozaki

     

  • 0 in reply to Nori Shinozaki
    TI__Mastermind 42545 points

    The device was designed to support the UDIMM standard for DDR3 dimms.  That standard has two sets of DDR3 clock pairs where the first is defined for a single rank DIMM and the second for dual rank DIMM.  That's the reason for the second clock pair on the part.  Using a single clock pair for all the parts on a single rank is necessary for proper fly-by routing of the address, command and clock signals.  Splitting the clock between groups of the DDRs on the same rank would change the timing of the clock relative to the address and command signals.