AM67A: SOC Package delay

Do you also have the RLC-data for the DDR pins? It would improve the Sigrity simulation of these nets.

Hello,

Yes, if you search for the word "matrix" in the ibis model you'll find the following:

Model Data]
|
| The resistance matrix for this package has no coupling
|
[Resistance Matrix] Banded_matrix
[Bandwidth] 0
[Row] H17
0.032209

<snip>

|
| The inductance matrix has sparse coupling
|
[Inductance Matrix] Sparse_matrix
[Row] H17
H17 4.35728e-10
G19 1.09632e-11

<snip>

|
| The capacitance matrix has sparse coupling
|
[Capacitance Matrix] Sparse_matrix
[Row] H17
H17 7.79462e-13

Regards,

Kyle

Thanks!
I have only worked with lumped RLC-pin IBIS parameters before, but I see that the matrix representations are also describing the coupling between different pins. Correct?

Out of curiosity, I looked at DDR_A0 which is pin L4. According to the matrices, it has no other capacitive coupling than to GND, 0.98 pF. The inductance matrix indicates a self inductance of 1.76 nH. It also has a bunch of other inductive couplings to nearby pins (that I don't know how to handle right now).

Calculating the propagation delay of this LC-circuit, I get sqrt(0.98 pF * 1.76 nH) = 41.5 ps. The pin delay file you linked above however states a delay of only 20.6 ps on DDR_A0. I can't see why they don't match. Could you please help me understand?

I have now checked with other IBIS models and the Matrix values are always matching the stated pin parasitics and delays at the [Pin] section of the file. So using the Matrix values should be correct.
Then we have a discrepancy here. What delays are reliable? The package delay report you posted on top of this thread or the IBIS file downloaded from the product page?

Ludvig,

I've uploaded a s-param model for the DDR package.  This should be more accurate than both the matrix model in the original IBIS file and the net length xls.  You can refer to this appnote for details on how to use these models

Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F).

J722S_DDR_pkg_s-param_model_20240816.zip

Regards,

Kyle